Au Optronics Corporation

Auo Corporation

Chung-Lin Fu

Yu-Hsin Ting

Wei-Chun Hsu

Nan-Ying Lin

Pei-Hua Chen

Tsao-Wen Lu

Shih-Hsi Chang

Chung-Hung Chen

Chen-Ming Chen

Chin-Tang Chuang

I-Fang Chen

Szu-Chieh Chen

Da-Wei Fan

Fu-Yuan Liou

Shu-Huan Hsieh

Yi-Xuan Hung

Wei-Chih Lee

A signal control method suitable for a touch screen is provided. The signal control method comprises: switching a plurality of scan lines to an enabling voltage level sequentially in a display stage; turning on a plurality of switches sequentially to transmit a plurality of display data to a plurality of data lines when a first scan line of the plurality of scan lines is in an enabled voltage level, wherein a first switch of the plurality of switches is coupled to a first data line of the plurality of data lines, and the first data line corresponds to one of a plurality of dummy lines in a vertical direction, when the first scan line is in the enabled voltage level, the first switch is turned on after other switches are turned on; and setting the plurality of dummy lines to a touch voltage in a touch stage.

Signal control method, controller chip and touch screen

A pixel array substrate includes signal lines, pixel structures, a driving element, a first fan-out trace and a second fan-out trace. The first fan-out trace includes a first segment connected to the driving element, a second segment connected to the first segment, and a third segment connected to the second segment. In the first fan-out trace, the sheet resistances of the first segment and the third segment are smaller than sheet resistance of the second segment. The second fan-out trace includes a first segment connected to the driving element and a second segment connected to the first segment. In the second fan-out trace, the first segment and the second segment are disposed correspondingly to the first segment and the two second segment and third segment, respectively. In the second fan-out trace, the sheet resistance of the second segment is less than the sheet resistance of the first segment.

Pixel array substrate

A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.

Liquid crystal display and test circuit thereof

A fingerprint identification device includes a backlight module and a sensing module. The sensing module is disposed on the backlight module. The sensing module includes a plurality of light sensing units and a plurality of light converting units. Each of the light converting units is disposed on a respective one of the light sensing units. The backlight module emits a first color light, the first color light passes through gaps between the light sensing units and then is reflected to the light converting unit, and the light converting unit converts the first color light into a second color light, such that the light sensing unit senses the second color light.

Fingerprint identification device

A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Shift register

A driving method for a display panel is provided. The display panel includes at least a first common signal line, at least a second common signal line and a plurality of pixels arranged as a pixel array. The pixel array includes a first pixel row and a second pixel row electrically connected to the first common signal line and the second common signal line, respectively. The driving method includes steps of: generating a first AC common signal; generating a second AC common signal, wherein the first AC common signal and the second AC common signal are inverse to each other; and providing the first and second AC common signal to the first and second pixel rows through the first and second common signal lines, respectively, by way of N-frame switch, wherein N is a positive integer.

Driving method for display panel

A gate driver includes a plurality of shift registers and a plurality of cutting units. Each of the shift registers is configured for outputting a shift register signal according to a clock signal of the each of the shift register sequentially. Each of the shift register signals has a working period and the two working periods of the two adjacent shift register signals overlap each other. Each of the cutting units is coupled to a respective one of the shift registers. The cutting unit corresponding to the Nth shift register is configured for cutting a part of the working period from the shift register signal of the Nth shift register to generate a gate driving signal according to the clock signal of the (N&#x2212;1)th or (N+1)th shift register, such that working periods of the gate driving signals are staggered. N is a positive integer larger than two.

Double sided single drive gate driver with reduced dark spots

A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Shift register and method of controlling the shift register

A display device includes multiple pixels, a gate driver and a data driver. Each pixel includes a transistor and a pixel capacitor electrically coupled to the transistor. The gate driver is configured to turn on the transistor of a first pixel for one time during a first turn-on period of multiple turn-on cycles of a frame cycle of a frame displayed by the display device. The data driver is configured to charge the pixel capacitor of the first pixel via the transistor of the first pixel to a first over-charge voltage and a data voltage during an over-charge period and a recovery period of the first turn-on period. The first over-charge voltage is different from the data voltage. A method for driving the display device is also provided.

Display device and driving method thereof

A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Display panel having a plurality of multiplexers for driving a plurality of first driving switches and a plurality of second driving switches

In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Display with multiplexer feed-through compensation and methods of driving same

An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Active liquid crystal display panel

A data line driving method adapted in a display panel driver circuit is provided. The display panel driver circuit comprises a plurality rows of gate lines and a plurality of data driver stages each corresponding to a data line group, wherein the data line driving method comprises the steps of: turning on the data driver stages in a first sequential order to input a first frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a first frame period; and turning on the data driver stages in a second sequential order which is opposed to the first sequential order to input a second frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a second frame period; wherein the first and the second frame period are two interlaced periods next to each other.

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Hsin-Chu, Taiwan

Chung-Lin Fu