Lsi Corporation

Skhynix Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Nyquist Semiconductor Limited

Innogrit Technologies Co., Ltd.

Chung-Li Wang

Shaohua Yang

Zongwang Li

Fan Zhang

Yang Han

Shu Li

Lei Chen

Johnson Yen

Jie Chen

Changyou Xu

Yuan-Mao Chang

Anatoli Aleksandrovich Bolotov

Dan Liu

Wu Chang

Qi Zuo

Wei Zhang

Bruce Alexander Wilson

Qi Qi

Lingqi Zeng

Weijun Tan

Mikhail I Grinchuk

Yi-Min Lin

Zining Wu

Naveen Kumar

Aman Bhatia

Haitao Xia

Ming Jin

Yu Kou

Lav D Ivanovic

Abhiram Prabhakar

Kaitlyn T Nguyen

Kaichi Zhang

Wei-Hao Yuan

Chun Hok Ho

Jingyu Kang

Yibo Zhang

Cai Wang

Keklik Bayam Alptekin

Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.

Systems and methods for decoding error correcting codes

Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit.

Systems and methods for decoding error correcting codes with self-generated LLR

Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a first decoding on a codeword using a first decoder, determining a number of satisfied check nodes and a number of unsatisfied check nodes for a symbol value of the codeword for a decoding result of the first decoding, generating a soft log-likelihood ratio (LLR) for the symbol value based on the number of satisfied check nodes and the number of unsatisfied check nodes, and performing a second decoding using a second decoder with the soft LLR as an input to the second decoder.

Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a soft decision decoding on a codeword, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a reliability determination for each hard decision and performing a hard decision decoding using the hard decision for each bit and reliability determination for each hard decision.

Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.

Efficient encoder based on modified RU algorithm

A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.

Reliability-assisted bit-flipping decoding algorithm

Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.

Cyclically interleaved XOR array for error recovery

A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

One-shot decoder for two-error-correcting BCH codes

Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.

Techniques for adaptive LDPC decoding

A first physical location is read to obtain read data. Error correction decoding is performed on the read data to obtain error-corrected data where the error-corrected data includes first error-corrected metadata. Error correction encoding is performed on a first random sequence combined with a second random sequence, concatenated with second metadata. Error correction encoding is also performed on a sequence of zeros concatenated with the first error-corrected metadata to obtain second encoded data. The error-corrected data, the first encoded data, and the second encoded data are summed to obtain migrated data, which is stored at a second physical location.

Encoder by-pass with scrambler

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit.

Systems and methods for local iteration randomization in a data decoder

The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

System and method for check-node unit message processing

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. In one embodiment a data processing system includes a skip control circuit operable to skip re-application of a data decode algorithm to a portion of a codeword where at least the number of unsatisfied checks for the portion is zero.

Systems and methods for skip layer data decoding

A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

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San Jose, CA, United States of America

Chung-Li Wang