Macronix International Co., Ltd.

Chung-Kuang Chen

Chun-Hsiung Hung

Han-Sung Chen

Yi-Te Shih

Ful-Long Ni

Chia-Ching Li

Chien-Fu Huang

Chia-Ming Hu

Shuo-Nan Hung

Yi-Ting Lai

Chih-He Chiang

Hsiang-Pang Li

Chun Hsiung Hung

Shin-Jang Shen

Tzeng-Huei Shiau

Chang-Ting Chen

Han Sung Chen

Jer-Hao Hsu

Chung-Hsiung Hung

Chun-Shiung Hung

Ming-Yi Chang

Chien-Ping Tai

A three-dimensional memory structure is provided and including a memory array, including a first and a second sub-arrays, each having a first selection line, plural word lines, and a second selection line; a connection structure, including plural connection areas, and at least one of extension structures of the first selection line, the plural of word lines, and the second selection line is coupled to a corresponding connection area of the plurality of connection areas; a pass gate set, arranged under the connection structure and between the first and the second sub-arrays, the pass gate set including plural pass gates, and, the word lines and the second selection line, and the pass gates are respectively coupled to the corresponding connection areas; and a drive circuit, coupled to the pass gate set, and disposed under the connection structure.

3D memory structure and circuit

An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.

Temperature sensor and memory device having same

A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.

Capacitor string structure, memory device and electronic device

A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.

Metal capacitor

A level shifter circuit to convert a first signal having an input voltage range V1 to a level shifted output having an output voltage range V2 includes an NMOS depletion mode transistor having a drain terminal connected to an output range upper-level supply node, a source connected to an intermediate node and a gate connected to an output node, a PMOS enhancement mode transistor having a drain terminal connected to the output node, a source connected to the intermediate node and a gate connected to an input node, and an NMOS enhancement mode transistor having a drain terminal connected to the output node, a source connected to an output range lower-level supply node and a gate connected to the input node.

Level shift circuit

A memory device includes a memory cell array, a current detector and a controller. The memory cell array has a plurality of memory cell strings coupled to a common source line. The current detector detects a circulating current on the common source line or a power end of a page buffer. The controller is configured to: during a program operation, perform a first program operation on a plurality of first memory cells corresponding to logic 0 according to a first program verify voltage, and perform a second program operation on a plurality of second memory cells corresponding to logic 1 according to a second program verify voltage, where the first program verify voltage is different from the second program verify voltage; and provide a read voltage to the memory cell strings during a read operation, and sense the circulating current based on a read current reference value.

Memory device and control method thereof

A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.

Fast interval read setup for 3D NAND flash

A memory cell strings respectively have a plurality of string selecting switches, wherein the plurality of string selecting switches are controlled by a string selecting control voltage. The string selecting control voltage generator is coupled to the memory cell strings, and generate the string selecting control voltage according to an ambient temperature during a writing operation performed on the plurality of memory cell strings. Wherein each of the plurality of memory cell strings is inhibited, programmed or quick pass written during the writing operation.

Flash memory device and control method

A memory device, a source line voltage adjuster and a source line voltage adjusting method thereof are provided. The source line voltage adjuster includes an operation amplifier, a current drainer and a current generator. The operation amplifier includes a first input end coupled to a common source line and a second input end for receiving a reference voltage. The operation amplifier generates an bias voltage. The current drainer drains a drain current from the common source line according to the bias voltage. The current generator provides an output current for the common source line. The current generator generates a first current according to the bias voltage, and generates a second current according to a reference current. The current generator generates the output current according to a difference of the second current and the first current.

Memory device, source line voltage adjuster and source line voltage adjusting method thereof

A memory device comprises a memory cell array with memory cells arranged in a cell string coupled to a metal bit line, a sense amplifier for providing a sensing current to the memory cell array, and a memory controller for controlling the sense amplifier to provide the sensing current to access data during a memory access cycle. The memory controller performs operations comprising: during a pre-charging stage of the memory access cycle, providing a pre-charging voltage to the sense amplifier to drive the sense amplifier such that a particular voltage is provided to the memory cell array; during a first sensing stage, providing the pre-charging voltage to the sense amplifier; and during a second sensing stage, providing a sensing voltage to drive the sense amplifier such that the particular voltage provided to the memory cell array is maintained.

Sensing a memory device

A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.

The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Clock integrated circuit

A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.

Memory device and memory controlling method

One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.

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Hsinchu, Taiwan

Chung-Kuang Chen