Cirrus Logic Inc.

Semtech Corporation

Robert Boschgmbh

Uhnder, Inc.

Chung-Kai Chow

Wai Laing Lee

Edwin De Angel

Lei Wang

Joel W Page

Hong Helena Zheng

John L Melanson

Monier Maher

Marius Goldenberg

Frederick Rush

Otto A Schmid

Karl Ernesto Thompson

Ammisetti Prasad

Jeffrey Blackburn

A multi-chip MIMO radar system includes a plurality of transmitters and a plurality of receivers. Each of the pluralities of transmitters and receivers are arranged across a plurality of chips. The multi-chip MIMO radar system is configured to provide an exemplary chip synchronization such that the transmitters and receivers of each chip of the radar system are synchronized with the transmitters and receivers of every other chip of the radar system.

Multi-chip synchronization for digital radars

A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

Segmented chopping amplifier

A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

Network synchronization

A precision measurement unit (PMU) includes a force amplifier selectively providing either a forcing voltage or a forcing current to a device under test via an output force terminal. A low limit voltage clamp and a high limit voltage clamp are operatively coupled to the output force terminal. The low and high limit voltage clamps are each responsive to user programming to define respective low and high voltage limits at the output force terminal. Upon detection of a reversal of said user programming, the operation of the low and high limit voltage clamps is disabled. More particularly, a comparator is adapted to compare the low and high voltage limits and provide a corresponding disabling signal if the high voltage limit is lower than the low voltage limit.

Precision measurement unit having voltage and/or current clamp power down upon setting reversal

A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

Power on reset techniques for an integrated circuit chip

A high-impedance mode is provided for an output of a precision measurement unit (PMU). The PMU includes an output amplifier that provides a forcing voltage or current to a device under test. When the high-impedance mode is activated, the output amplifier is decoupled from an output terminal of the PMU and the output amplifier is disabled. This prevents the voltage on the output terminal from rising in an uncontrolled manner, and prevents current spikes from forming on the output terminal when connected to a device under test. The high-impedance mode is deactivated to permit connection of the PMU to another device under test by re-coupling the output amplifier to the output terminal and enabling operation of the output amplifier.

High-impedance mode for precision measurement unit

A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Sinc filter using twisting symmetry

A data acquisition system has a central station connected to a plurality of nodes over a network. Each node is connected to receive signals from one or more sensors ad each is configured to have substantially the same transmission delay to said central station. The central station is configured to notify all nodes of an event time at which a data event, such as a seismic shot, occurred.

System and techniques for seismic data acquisition

A phase shifter is implemented using a polyphase filter. The filter is preferably a linear phase Finite Impulse Response (FIR) filter. The amount of delay imparted by the phase shifter is determined by a particular set of coefficients selected from a plurality of such coefficients. Storage requirements are reduced by taking advantage of symmetries in the coefficients for the filters. Memory requirements are further reduced by partitioning the polyphase filter into two polyphase filters and using one to set a rough delay amount and the other to set a fine delay amount between rough delay amount settings. The particular amount of delay may be set by an external synchronization signal.

Linear phase FIR sinc filter with multiplexing

A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4,order, 5 tap sinc filters, a 4,order, 9 tap sinc filter; a 5,order, 6 tap sinc filter and a 6,order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Sinc filter with selective decimation ratios

A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Noise management using a switched converter

A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y&plus;Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y&plus;Accumulator&plus;round is negative; and (5) determines a correct carry bit based on the other determinations.

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Austin, TX, United States of America

Chung-Kai Chow