Silicon Integrated Systems Corporation

Chung-Ju Wu

Wei-Feng Lin

Chen-Wen Tsai

Kuei-Chen Liang

Wei-Chi Liu

Yin-Chieh Hsueh

This disclosure presents a heat dissipation mechanism, which conducts generated heat of a thermal device to the housing of an electronic apparatus by a metal piece fastened between the thermal device and electronic apparatus, and then dissipates heat into the air through multiple holes opened over an apparatus shell. Besides, the presented mechanism is also suitable to mini-size, portable electronic apparatus to solve the thermal dissipation technique thereof.

Heat dissipation mechanism for electronic apparatus

The present invention provides a heat sink device for the package device to improve the heat dissipating efficiency. The heat sink device includes a first heat sink assembly and a second heat sink assembly. The first heat sink assembly has a first heat dissipating structure, a second heat dissipating structure positioned above first the heat dissipating structure, at least two thermal supports on the backside of the first heat sink assembly and a thermal block on the backside of the first heat sink assembly. The second heat sink assembly has a protruding structure and at least the openings. The first heat sink assembly is fixed with the second heat sink assembly to form a heat sink device by the combination of the thermal supports and the openings. The first heat sink assembly and the second heat sink assembly are attached to the integrated circuit device separately by the thermal block and the protruding structure. This heat sink device provides several heat dissipating pathes by the second heat dissipating structure, the thermal supports, the thermal block, and protruding structure. Therefore, the heat dissipation efficiency of the heat sink device is improved.

Ball grid array package with heat sink device

A die paddle for receiving an integrated circuit die in a plastic substrate. The die paddle is defined by a copper film on the plastic substrate and comprises a plurality of via holes through the plastic substrate, a plurality of opening through the copper film, and a gold-containing ring formed on the peripheral portion of the copper film. The outermost openings (and/or the outermost via holes) and the gold-containing ring are separated by a distance of about 1 to about 20 mils.

Die paddle for receiving an integrated circuit die in a plastic substrate

A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

Chip-packaging substrate

An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal wire bonding is coupled to the signal connection point and the signal pad. Two shielding wire bondings are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal wire bonding. The signal trace line is set on the substrate and coupled to the signal connection point. The power ring circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.

Integrated circuit bonding device and manufacturing method thereof

A flip chip package structure. The structure includes a substrate, an IC chip electrically connected to the substrate through a plurality of conductive bumps, encapsulant between the substrate and IC chip, and an electrically protective device. The substrate has interior wiring, a plurality of first contacts arranged at a predetermined pitch among each other on a surface, and a trace line area beyond the first contacts on the surface. The electrically protective device has a protruding part covering the IC chip, and an extending part extending over the surface of the substrate with a gap as large as 40 mil. The extending part further covers the trace line area, and connects to the surface of the substrate using a fixing material.

Flip chip package structure

An integrated circuit package capable of improving signal quality is disclosed. The integrated circuit package comprises a first substrate, an integrated circuit chip attached on the first surface of the first substrate. This integrated circuit package further comprises a plurality of external terminals mounted on the first substrate and a plurality of first bonding pads mounted on the edge portion of the first surface of the first substrate and respectively connected to the corresponding external terminals. Also, the integrated circuit package further comprises a second substrate and a plurality of second bonding pads mounted on the second surface of the second substrate and connected to the first bonding pads formed on the first substrate. Furthermore, this integrated circuit package further comprises a plurality of passive components disposed on the second substrate.

Integrated circuit package capable of improving signal quality

A multi-layered substrate having built-in capacitors is disclosed. The substrate comprises at least one high permittivity of dielectric material filled in the through holes between the power plane and the ground plane so as to form capacitors. The built in capacitors are to decouple high frequency noise due to the voltage fluctuation.

Multi-layered substrate with a built-in capacitor design and a method of making the same

A bond pad structure and a method of fabricating such structure are disclosed in the invention. The bond pad structure is formed over a predetermined area defined on a semiconductor substrate. The bond pad structure includes at least two metal layers formed over the predetermined area and at least one sub-structure combination layer which each is formed over the predetermined area and formed between two corresponding first metal layers. Each sub-structure combination layer includes a dielectric layer formed over the predetermined area, formed-through via openings with special disposition on the dielectric layer, a first diffusion barrier layer formed over the dielectric layer and the sidewalls and bottom of the via openings, a metal material filled into the via openings to form via plugs, and a second diffusion barrier layer formed over the first diffusion barrier layer and via plugs. Due to special disposition of via plugs and well adhesion between metal layer and diffusion barrier layers, the bond pad structure, according to the invention, can prevent form damage possibly induced during subsequent probe test procedure and wire bonding process.

Bond pad structure and its method of fabricating

An apparatus for reducing an electrical noise inside a ball grid array package is disclosed. The apparatus mainly comprises a substrate, a plurality of solder balls and a plurality of inside-connected capacitors. The substrate includes a contact layer, a power plane and a ground plane. The plurality of solder balls are fixed on the contact layer. The plurality of inside-connected capacitors are fixed on the contact layer, and a conductive glue is used to electrically connect the capacitors to the power plane and ground plane to reduce the electrical noise between the power plane and ground plane.

Apparatus for reducing an electrical noise inside a ball grid array package

A multi-layered substrate having built-in capacitors is used to decouple high frequency noise generated by voltage fluctuations between a power plane and a ground plane of a multi-layered substrate. At least one kind of dielectric material, which is filled in through holes between the power plane and the ground plane, with high dielectric constant is used to form the built-in capacitors.

Multi-layered substrate with a built-in capacitor design

A tray is adapted to receive a plurality of ball grid array devices therein, and includes a base plate having a device-receiving portion and a peripheral portion around the device-receiving portion. The device-receiving portion has a top side formed with a device-receiving recess. The top side of the device-receiving portion is further formed with a partition unit in the device-receiving recess for dividing the device-receiving recess into a plurality of cavities adapted for receiving the ball grid array devices respectively therein. The device-receiving portion further has a bottom side formed with a plurality of openings. Each of the openings is aligned with a corresponding one of the cavities and is adapted to receive an array of ball contacts formed on a bottom side of the ball grid array device that is disposed in the corresponding one of the cavities therein. The openings are grouped into a set of first openings remote from the peripheral portion and a set of second openings surrounding the first openings and adjacent to the peripheral portion. Guard strips are formed on the bottom side of the device-receiving portion and are disposed solely and respectively in the second openings.

Growing community of inventors

Kaohsiung, Taiwan

Chung-Ju Wu