Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Vanguard International Semiconductor Corporation

Lam Research Corporation

Parabellum Strategic Opportunities Fund LLC

Chung-Ju Lee

Tien-I Bao

Wei-Hao Liao

Chih Wei Lu

Shau-Lin Shue

Hsi-Wen Tien

Cheng-Hsiung Tsai

Hsin-Chieh Yao

Chih-Wei Lu

Tsung-Min Huang

Pin-Ren Dai

Yung-Hsu Wu

Yu-Teng Dai

Chien-Hua Huang

Ru-Gun Liu

Tsai-Sheng Gau

Chieh-Han Wu

Hsiang-Huan Lee

Yu-Sheng Chang

Hai-Ching Chen

Ming-Feng Shieh

Chia-Tien Wu

Chun-Kuang Chen

Yung-Sung Yen

Tsung-Jung Tsai

Sunil Kumar Singh

Chih-Ming Lai

Shih-Ming Chang

Kuei-Shun Chen

Ta-Ching Yu

Jeng-Horng Chen

Shinn-Sheng Yu

Chih-Tsung Shih

Tai-I Yang

Wei-Chen Chu

Hwei-Jay Chu

Jyu-Horng Shieh

Ken-Hsien Hsieh

Hsiang-Ku Shen

Chia-Ying Lee

Hsin-Ping Chen

Chih-Ning Wu

Zhao-Cheng Chen

Carlos H Diaz

Fu-Liang Yang

Anthony Yen

Ming-Han Lee

Tzu-Hui Wei

David Dai

Chung-Te Lin

Chien-Min Lee

Hsin-Yen Huang

Po-Chao Tsao

Tai-Yen Peng

Kuan-Yang Liao

Cherng-Shiaw Tsai

Ming-Tsung Chen

Wei-Tsun Shiau

Yu-Lan Chang

Chang-Chi Huang

Yi-Yiing Chiang

Chok Ho

Pei-Yi Lin

Kuo-Lung Tang

Chin-Hsiang Lin

Tsung-Lin Lee

Chih-Hao Chang

Shin-Yi Yang

Liang-Gi Yao

Tsung-Yu Chen

Hung-Chang Hsieh

Yen-Cheng Lu

Sey-Ping Sun

Ming-Shih Yeh

Ming-Hui Weng

Ing-Ruey Liaw

Bo-Jiun Lin

Hsien-Chang Wu

Shih-Kang Fu

Yin-Pin Wang

Wei-Ray Lin

Ming Han Lee

Yue-Feng Chen

Yu-Fu Lin

Ming-Hong Kuo

Yeur-Luen Tu

Chao-An Jong

Wen-Jya Liang

An-Dih Yu

Hsin Tai

Yuh-Sheng Chern

Jhy-Weei Hsia

Meow-Ru Hsu

Meow-Ru Sheu

An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Semiconductor device structure and methods of forming the same

An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure. The MRAM device further includes a first etch stop layer on the spacers. A bottommost surface of the first etch stop layer covers a topmost surface of the spacers. In addition, the MRAM device includes a top electrode via on the top electrode and the first etch stop layer.

Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via

Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Self-aligned via for interconnect structure

The present disclosure relates to an integrated chip including a substrate. A first conductive wire is within a first dielectric layer that is over the substrate. A first etch-stop layer is over the first dielectric layer. A second etch-stop layer is over the first etch-stop layer. A conductive via is within a second dielectric layer that is over the second etch-stop layer. The conductive via extends through the second etch-stop layer and along the first etch-stop layer to the first conductive wire. A first lower surface of the second etch-stop layer is on a top surface of the first etch-stop layer. A second lower surface of the second etch-stop layer is on a top surface of the first conductive wire.

Dual etch-stop layer structure

An interconnect structure includes a dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.

Interconnection structure and methods of forming the same

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Method and structure of cut end with self-aligned double patterning

Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.

Self-assembled dielectric on metal rie lines to increase reliability

A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Methods of etching metals in semiconductor devices

The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

Self-aligned interconnect structure

In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Dielectric on wire structure to increase processing window for overlying via

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Method and structure for semiconductor device having gate spacer protection layer

A memory device includes a bottom electrode, a tunneling junction disposed over the bottom electrode, and a top electrode disposed over the tunneling junction. The top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer. The first and second top electrode layers include different material compositions. The first top electrode layer is thinner than the tunneling junction, and the second top electrode layer is thicker than the tunneling junction.

Structure and method for an MRAM device with a multi-layer top electrode

In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that includes a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounding by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.

Interconnect conductive structure comprising two conductive materials

A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.

Magnetic tunnel junction devices

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Hsinchu, Taiwan

Chung-Ju Lee