Au Optronics Corporation

Wistron Neweb Corporation

Ses Rfid Solutions Gmbh

Chung-Hung Chen

Shyh-Bin Kuo

Hsiang-Chi Cheng

Yi-Cheng Lai

Chin-Tang Chuang

Kuo-Hsiang Chen

Yi-Jan Chen

Sin-Jie Wang

Yi-Chen Lu

Hsu-Chi Li

Boy-Yiing Jaw

Yu-Chih Wang

Shih-Hsing Hung

Ya-Ting Lin

Chih-Sen Hsieh

Shih-Hsien Yang

Chia-Hao Chang

Chih-Ming Wang

Yu-Hsin Ting

Wei-Chun Hsu

Chung-Lin Fu

Martin Scattergood

Hsin-Yi Lai

Yen-Hua Hsu

Yi-Hung Chiu

Chia-Hsing Hsieh

A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Memory chip and operating method thereof

A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

Level shifter

An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.

Integrated circuit, wireless communication card and wiring structure of identification mark

A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.

Chip having a flexible substrate

An antenna device includes a substrate, a chip, and an antenna. The chip is disposed on the substrate, and the chip has at least two pads. The antenna is disposed on the substrate, and the chip is disposed between the substrate and the antenna. The antenna has a first bonding line segment and a second bonding line segment electrically connected to the at least two pads respectively. The first bonding line segment is located at an outermost coil of the antenna, and is disposed across a short side direction of the chip in a manner of completely covering one of the at least two pads. The second bonding line segment is located at an innermost coil of the antenna, and is disposed across the short side direction of the chip in a manner of completely covering another of the at least two pads.

Antenna device and manufacturing method thereof

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Voltage adjust circuit and operation method thereof

A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines.

Semiconductor chip

An electronic device, including an antenna, includes a pixel array, a control circuit, and a gate driver. The control circuit is coupled with the antenna, and configured to receive a RF signal from the antenna. The gate driver is coupled with the control circuit and the pixel array, and includes multiple shift registers. Each of the multiple shift registers is configured to output a scan signal to the pixel array. The control circuit is configured to output a triggering signal to a first-stage shift register of the multiple shift registers. When the control circuit receives the RF signal, the triggering signal has a triggering pulse. When the first-stage shift register receives the triggering pulse, the first-stage shift register outputs the scan signal having an enabling voltage level.

Electronic device and driving method thereof

A display system includes a pixel array, an antenna, a reader circuit, and a gate driver circuit. The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication. The reader circuit is coupled to the antenna and is configured to receive the RF signal. The gate driver circuit is coupled to the reader circuit and the pixel array. The reader circuit is further configured to generate a clock signal according to the RF signal and transmit the clock signal to the gate drive circuit. The gate driver circuit is configured to generate scanning signals according to the clock signal and transmit the scanning signals to the pixel array.

Display system

A radio-frequency device for a wireless communication device includes an antenna disposition area, a grounding unit, a first antenna and a second antenna. The first antenna includes a feed-in plate; a first radiating element, coupled to the feed-in plate and electrically connected to the grounding unit; and a metal branch, electrically connected to the grounding unit; wherein the grounding unit is shared by the first antenna and the second antenna, the feed-in plate is disposed in-between the metal branch and the first radiating element, and the metal branch is used for guiding a reflected signal generated from the second antenna to the metal branch so as to enhance isolations of the first antenna and the second antenna.

Radio-frequency device and wireless communication device for enhancing antenna isolation

A display device includes multiple pixels, a gate driver and a data driver. Each pixel includes a transistor and a pixel capacitor electrically coupled to the transistor. The gate driver is configured to turn on the transistor of a first pixel for one time during a first turn-on period of multiple turn-on cycles of a frame cycle of a frame displayed by the display device. The data driver is configured to charge the pixel capacitor of the first pixel via the transistor of the first pixel to a first over-charge voltage and a data voltage during an over-charge period and a recovery period of the first turn-on period. The first over-charge voltage is different from the data voltage. A method for driving the display device is also provided.

Display device and driving method thereof

An antenna structure is provided, including a first radiator, a second radiator, a second coupling portion and a switch Circuit. The first radiator includes a feed portion and a first radiator body. The second radiator includes a first coupling portion, a second radiator body and a ground portion. The first coupling portion is connected to a first end portion of the second radiator body. The ground portion is connected to the second radiator body. At least a portion of the first radiator body is located between the first coupling portion and the second coupling portion. When the antenna structure is in a first mode, the switch circuit forms an electric path between the second radiator and the second coupling portion, and when the antenna structure is in a second mode, the switch circuit removes the electric path between the second radiator and the second coupling portion.

Growing community of inventors

Hsinchu, Taiwan

Chung-Hung Chen