Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Hua Fei

Bao-Ru Young

Harry Chuang

Jin-Aun Ng

Chien-Liang Chen

Maxi Chang

Wen-Chin Yang

The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

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Hsinchu, Taiwan

Chung-Hua Fei