Nxp B.v.

Chung Hsiung Ho

Wen-Hsuan Lin

James Raymond Spehar

Richard Te Gan

Chih Hung Chang

Tsung Nan Lo

Wayne Hsiao

Chia Hao Kang

Ju-Hsuan Ko

A packaged semiconductor device has a conductive film that covers a first major surface and surrounding side surfaces of an integrated circuit die. The conductive film provides five-sided shielding of the integrated circuit die. A metal heat sink may be attached to an exposed major surface of the conductive film for dissipating heat generated by the die.

Semiconductor device with conductive film shielding

In a die-substrate assembly, a copper inter-component joint is formed by bonding corresponding copper interconnect structures together directly, without using solder. The copper interconnect structures have distal layers of (111) crystalline copper that enable them to bond together at a relatively low temperature (e.g., below 300&#xb0; C.) compared to the relatively high melting point (about 1085&#xb0; C.) for the bulk copper of the rest of the interconnect structures. By avoiding the use of solder, the resulting inter-component joint will not suffer from the adverse IMC/EM effects of conventional, solder-based joints. The distal surfaces of the interconnect structures may be curved (e.g., one concave and the other convex) to facilitate mating the two structures and improve the reliability of the physical contact between the two interconnect structures. The bonding may be achieved using directed microwave radiation and microwave-sensitive flux, instead of uniform heating.

Solderless inter-component joints

Embodiments of a method for packaging Integrated Circuit (IC) dies and an IC device are described. In an embodiment, a method for packaging IC dies involves creating openings on a substrate, where side surfaces of the openings on the substrate are covered by metal layers, placing the IC dies into the openings on the substrate, applying a second metal layer to the substrate, where the IC dies are electrically connected to at least a portion of the second metal layer, and cutting the substrate into IC devices.

IC packaging method and a packaged IC device

A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.

Multi-via redistribution layer for integrated circuits having solder balls

Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.

Integrated circuits and methods therefor

A semiconductor device includes a semiconductor die having a top side and a bottom, active side. During assembly of the semiconductor device, a metal film is sputtered over the top and side surfaces of the die, and then a mold compound is formed over the metal film. The metal film can provide both heat dissipation and EMI shielding. The device may be assembled using a wafer level assembly process.

Wafer level package with EMI shielding

A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer covers at least the top surface and the sidewalls of the die. A thickness of the first protective layer on the sidewalls near the top surface is greater than a thickness of the first protective layer on the sidewalls die near the bottom surface.

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Kaohsiung, Taiwan

Chung Hsiung Ho