Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Hsing Wang

Kuo-Nan Yang

Yuan-Te Hou

Hiranmay Biswas

Chin-Shen Lin

Yen-Hung Lin

Huang-Yu Chen

Lee-Chung Lu

Yi-Kan Cheng

King-Ho Tam

Yen-Pin Chen

Chien-Ju Chao

Jerry Chang-Jui Kao

Yi-Chuin Tsai

Chou-Kun Lin

Wen-Hao Chen

Meng-Xiang Lee

Po-Hsiang Huang

Sheng-Hsiung Chen

Sung-Yen Yeh

Wan-Yu Lo

Li-Chung Hsu

Chin-Hsiung Hsu

Li-Chun Tien

Cheng-I Huang

Hsiao-Shu Chao

Tai-Yu Cheng

Fong-Yuan Chang

Ho Che Yu

Tzu-Hen Lin

Ravi Babu Pittu

Yung-Chin Hou

Chin-Chou Liu

Jerry Chang Jui Kao

Ming-Hsien Lin

Chun-Chen Chen

Chung-Min Fu

Shao-Huan Wang

Cliff Hou

Shih-Hsien Yang

Chi Wei Hu

Li Chung Hsu

Nitesh Katta

Jiann-Tyng Tzeng

Hui-Zhong Zhuang

Chin-Chang Hsu

Ke-Ying Su

Ting Yu Chen

Chi-Yeh Yu

Chung-Kai Lin

Jian-Yi Li

Fang-Yu Fan

Chun-Hui Tai

Lie-Szu Juang

Hung-Jen Liao

Kam-Tou Sio

Ching-Wei Wu

Jui-Feng Kuan

Wen-Ju Preet Yang

Hong-Chen Cheng

Jui-Che Tsai

Chih-Hsiang Yao

Yung-Chen Chien

Jung-Hsuan Chen

Zhe-Wei Jiang

John Jianghann Lin

Kumar Lalgudi

Kai-Yun Lin

Hao-Tien Kan

Chih-Liang Chen

Shih-Wei Peng

Yi-Wei Chen

Stefan Rusu

Dian-Hau Chen

Charles Chew-Yuen Young

Yi-Hsun Chiu

Hsiang-Ku Shen

Hsien-Hsin Sean Lee

Gwan Sin Chang

Chih-Hung Wu

Shyh-Horng Yang

Meng-Kai Hsu

Wei-Hsiang Ma

Jhong-Sheng Wang

Tzu-Ying Lin

Wei-Pin Changchien

Chih-Cheng Chou

Ching-Shun Yang

Tsung-Han Wu

Min-Yuan Tsai

Shun-Li Chen

Huan Chi Tseng

Hung Lung Lin

Shu-Yi Ying

Yu-Jen Chang

Chia-Lin Cheng

Shou-En Liu

Ying-Yu Shen

Cheng-Yu Lin

Myron O Shak

A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.

Diagonal torus network

A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Semiconductor arrangement and method of making

Power grid of an integrated circuit (IC) is provided. A plurality of first power lines are formed in a first metal layer. A plurality of second power lines are formed in the first metal layer and parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. A plurality of third power lines formed in a second metal layer, and the third power lines are perpendicular to the first power lines. A plurality of fourth power lines are formed in the second metal layer and parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. Distances from each of the third power lines to two adjacent fourth power lines are different, and distances from each of the fourth power lines to two adjacent third power lines are the same.

Power grid, IC and method for placing power grid

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Conductor scheme selection and track planning for mixed-diagonal-manhattan routing

A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Block level design method for heterogeneous PG-structure cells

Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Systems and methods for context aware circuit design

Failure-in-time (FIT) evaluation methods for an IC are provided. Data representing a layout of the IC is accessed, and the layout includes a metal line and a plurality of vertical interconnect accesses (VIAs). The metal line is divided into a first sub-line with a first line width and a second sub-line with a second line width. A plurality of nodes are picked along the first and second sub-lines of the metal line. The metal line is divided into a plurality of metal segments based on the nodes. FIT value is determined for each of the metal segments to verify the layout and fabricate the IC. The first line width is greater than the second line width.

Method for evaluating failure-in-time

A method and system for manufacturing a circuit is disclosed. In some embodiments, the system includes: at least one processor configured to: generate a first timing library for a first set of circuit elements for a first set of input parameters based on device characteristics for each of the circuit elements in the first set of circuit elements, and storing the determined device characteristics in a database; and generating a second timing library for a second set of circuit elements for a second set of input parameters based on device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and a circuit generation system, coupled to the at least one processor, the circuit generation system configured to form a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

Circuit testing and manufacture using multiple timing libraries

A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.

System and computer program product for integrated circuit design

An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

Integrated circuit with mixed row heights

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Systems and methods for integrated circuit layout

A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.

Leakage analysis on semiconductor device

An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

Integrated circuit device and method

A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

Growing community of inventors

Baoshan, China

Chung-Hsing Wang