Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Hsien Chen

Chi-Wen Liu

Clement Hsingjen Wann

Yu-Lien Huang

Tung Ying Lee

Ting-Chu Ko

Chih-Sheng Chang

Shau-Lin Shue

Ming-Feng Shieh

Ling-Yen Yeh

Chun-Chieh Lin

Yi-Tang Lin

Chi-Yuan Shih

Minghsing Tsai

Meng-Chun Chang

Li-Chi Yu

Chih-Hao Chang

Shou-Zen Chang

A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.

System and methods for converting planar design to FinFET design

The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Fin structure of semiconductor device

A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.

Contact structure of semiconductor device

A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

Strained structure of a semiconductor device

A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions.

Buffer layer omega gate

The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a fin structure disposed over the substrate in the gate region. The fin structure includes a first semiconductor material layer as a lower portion of the fin structure, a semiconductor oxide layer as a middle portion of the fin structure and a second semiconductor material layer as an upper portion of the fin structure. The semiconductor device also includes a dielectric feature disposed between two adjacent fin structures over the substrate. A top surface of the dielectric feature located, in a horizontal level, higher than the semiconductor oxide layer with a distance d. The semiconductor device also includes a high-k (HK)/metal gate (MG) stack disposed in the gate region, including wrapping over a portion of the fin structure.

Semiconductor device with strain technique

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

A device includes a substrate, insulation regions extending into the substrate, and a semiconductor fin higher than top surfaces of the insulation regions. The semiconductor fin has a first lattice constant. A semiconductor region includes sidewall portions on opposite sides of the semiconductor fin, and a top portion over the semiconductor fin. The semiconductor region has a second lattice constant different from the first lattice constant. A strain buffer layer is between and contacting the semiconductor fin and the semiconductor region. The strain buffer layer includes an oxide.

MOS devices with strain buffer layer and methods of forming the same

A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

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Taipei, Taiwan

Chung-Hsien Chen