Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Hau Fei

Bao-Ru Young

Harry-Hak-Lay Chuang

Ming Zhu

Sin-Hua Wu

Chii-Horng Li

Harry Chuang

Jin-Aun Ng

Chien-Liang Chen

Wen-Chih Yang

Tze-Liang Lee

Chien-Hao Chen

Kuo-Tai Huang

Yen-Ru Lee

Hao-Ming Lien

Jun-Lin Yeh

Kang-Cheng Lin

Maxi Chang

Chi Hsin Chang

Chun Ming Lin

Ssu-Yu Li

A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

Semiconductor device and method of forming the same

A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

Methods for forming MOS devices with raised source/drain regions

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Method of fabricating a sealing structure for high-k metal gate

The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Method for making a semiconductor device having metal gate stacks

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Hsin-Chu, Taiwan

Chung-Hau Fei