Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Han Huang

Hung-Chih Lin

Mill-Jer Wang

Hao Chen

Ching-Nen Peng

Ching-Fang Chen

Wei-Hsun Lin

Chung-Sheng Yuan

Meng-lin Chung

Wen-Wen Hsieh

A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.

Apparatus for three dimensional integrated circuit testing

A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.

Test circuit and method

A circuit includes a stacked circuit layer, a plurality of test contact points, and a comparator. The stacked circuit layer includes a plurality of reference capacitors each having a reference capacitance. Each of the test contact points is electrically connecting to an under-test capacitor of an under-test module. The comparator compares the reference capacitance of one of the reference capacitors with an under-test capacitance of the under-test capacitor corresponding to one of the test contact points to measure a range of the under-test capacitance.

Capacitance measurement circuit and method

A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module.

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Taipei, Taiwan

Chung-Han Huang