International Business Machines Corporation

Macronix International Co., Ltd.

Globalfoundries Inc.

Qimonda North America Corporation

Other

Samsung Electronics Co., Ltd.

Globalfoundries U.S. 2 LLC

Marconix International Co., Ltd.

Chung H Lam

Matthew Joseph Breitwisch

Alejandro Gabriel Schrott

Bipin Rajendran

Hsiang-Lan Lung

Eric Andrew Joseph

Matthew Joseph BrightSky

David V Horak

Robert K Montoye

Steven J Holmes

Yu Zhu

Stephen Mark Rossnagel

Dharmendra S Modha

Mark Charles Hakey

Charles W Koburger, Iii

Daniel Joseph Friedman

Dennis Merton Newns

Chandrasekharan Kothandaraman

Ming-Hsiu Lee

Robert L Wisnieff

Dirk Pfeiffer

John Kenneth DeBrosse

Hon-Sum Philip Wong

Bahman Hekmatshoartabari

Viktors Berstis

Jeffrey Bowman Johnson

Xiao Hu Liu

Hemantha Kumar Wickramasinghe

Peter Juergen Klim

Robert L Bruce

James Spiros Nakos

Jose A Tierno

Donald M Kenney

Edward J Nowak

Jack Allan Mandelman

Toshiharu Furukawa

Erh-Kun Lai

Jed Hickory Rankin

Chung-Hsun Lin

Randy William Mann

Jan Boris Philipp

Kailash Gopalakrishnan

Howard L Kalter

Jonathan Zanhong Sun

Philip Joseph Oldiges

Kuan-Neng Chen

Devendra K Sadana

Ghavam G Shahidi

Claude Louis Bertin

John Edward Cronin

Tak H Ning

Vijay Narayanan

Chao-I Wu

Thomas Happ

Ramachandran Muralidhar

Eduard Albert Cartier

Yen-Hao Shih

Bomy A Chen

Frank Robert Libsch

Min Yang

Masatoshi Ishii

Richard Harold Boivie

Louis C Hsu

Jeffrey Scott Brown

Seiji Munetoh

Carl John Radens

Louis L Hsu

Arup Bhattacharyya

Shih-Hung Chen

Edmund Juris Sprogis

Robert K Leidy

James Albert Slinkman

Solomon Assefa

William Joseph Gallagher

Richard Quimby Williams

Nazmul Habib

Edward William Kiewra

Matthew R Wordeman

David Michael Fried

Michael Joseph Zierak

Jerome Brett Lasky

Lawrence Alfred Clevenger

William R Tonti

Oleg Gluschenkov

Kevin K Chan

Terence B Hook

Hendrik F Hamann

Sampath Purushothaman

Charalampos Pozidis

Leland Chang

Kenneth Parker Rodbell

Dana Lee

Kyu-hyoun Kim

Michele M Franceschini

Tze-Chiang Chen

Robert C Wong

Hyun K Lee

Jin Cai

Rajarao Jammy

Sarunya Bangsaruntip

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Integration of selector on confined phase change memory

One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Writing multiple levels in a phase change memory

Encryption engine with an undetectable/tamper proof private key in late node CMOS technology

Structures and methods for a multi-bit phase change memory are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Structures and methods for a multi-bit phase change memory, are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays

A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Integration of confined phase change memory with threshold switching material

A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

Phase change memory array with integrated polycrystalline diodes

A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

Method(s) and apparatuses for forming a phase change memory. A method includes: forming a crystalline phase-change layer at a first position in along a surface of a first semiconductor layer, and forming an amorphous phase-change layer at a second position along the surface of a second semiconductor layer, wherein the crystalline phase-change layer and the amorphous phase-change layer are in contact.

Method for manufacturing phase change memory

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Peekskill, NY, United States of America

Chung H Lam