Altera Corporation

Chung Fu

Michael Harms

Mark Andrew Banke

Zunhang Yu Kasnavi

Danh Dang

Aman Aflaki Beni

Ramraj Gottiparthy

A test probe may have signal and ground probe pins. During testing of an integrated circuit die, the signal and ground probe pins may contact pads on the die. A printed circuit board may have conductive pads and traces that route signals between a tester and the probe pins. The probe pins may be supported by a ring-shaped conductive epoxy support structure. The ground probe pins may be uninsulated within the conductive epoxy support structure, so that the ground probe pins are grounded along their length to the support structure. The signal probe pins may be insulated within the support structure. Coaxial cable shielding may be provided on the signal pins between an outer wall portion of the support structure and the printed circuit board.

Probe cards with minimized cross-talk

Method and apparatus are disclosed related to testing and testability of adaptive equalization circuitry. Where an equalization circuit is provided in an IC, a modified internal loopback provides a testing signal. A local comparator circuit with flexible connectivity offers analog signal testing analysis in conjunction with a low-cost external tester. Flexible use and connectivity of the comparator and external connection points, and block isolation circuitry make accurate, faster, and lower cost testing methods possible.

Method and apparatus for equalizer testing

A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This 'soft-wired' set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of the reconfigurable device. Additionally, the set of boundary scan registers only exists when a testing configuration is loaded into the reconfigurable device. When testing is complete, the testing configuration is erased and the functional blocks may implement other operations. Thus, the set of boundary scan registers consumes no additional chip area. Furthermore, as the set of boundary scan registers disappears after testing, a functional path enabling normal operation modes is unnecessary. Therefore, manually created functional test data is not needed. Instead, ATPG software can create test data from hardware descriptions of the IP core and the set of boundary scan registers.

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Sunnyvale, CA, United States of America

Chung Fu