Cadence Design Systems, Inc.

Springsoft Usa, Inc.

Chung-Do Yang

John Mario Wilkosz

Hoi-Kuen Lam

Hsi-Chuan Chen

Jeong-Tyng Li

Chih-Liang Cheng

Arnold Ginetti

Regis R Colwell

Jeffrey Markham

Jose A Martinez

Steven Riley

Khalid ElGalaind

Thomas Jordan

Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.

Method and system to implement topology integrity throughout routing implementations

Described is an improved approach to implement EM analysis, where the analysis can be performed early stages of the design process. Tree-routing is implemented using a structural routing solution, where an automatic routing mechanism is performed to generate a complete routing tree. That routing tree is then used to perform topology-driven EM analysis at various stages of the design process.

EM-compliance topology in a tree router

Described herein is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where a routing system is implemented to generate a complete routing tree. A user interface is provided that captures users' design intent about topology of an electrical design, and the routing system adheres to that user's design intent about the topology throughout a layout process for the electrical design.

User interface to implement topology integrity throughout routing implementations

Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree, and specific portions of the design are routed individually from other portions of the design.

Tree-routing for specific areas of an electronic design

A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design

Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

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Saratoga, CA, United States of America

Chung-Do Yang