Via Technologies, Inc.

Chung-Ching Huang

Chien-Ping Chung

Kuo-Han Chang

Yeh Cho

Wen-Juin Huang

Jing-Rung Wang

Tony Ho

Donna Lim

Norman Chung

Kuan-Jui Ho

Jui-Ming Wei

Chung-Che Wu

Ta-Chuan Liu

Chin-Fa Hsiao

Hao-Lin Lin

Chin-Hwaun Wu

Chin-Han Chang

Chun-Wei Chan

Yao-Wen Tang

Liang-Min Lee

Jia-Hung Wang

Tzu-Chiang Chiu

Chih-Nan Lo

Wen Juin Huang

Hao Lin Lin

Tai-Yu Lin

An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor.

Electronic device and secure boot method

An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Fast switching between multiple operating systems using standby state

A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data.

Computer system for processing data in non-operational state and processing method thereof

A computer system and a power-management method thereof are provided. The computer system has an image-reading mode, a first power-management mode and a second power-management mode, and the computer system operating in the second power-management mode consumes less power than it consumes in the first power-management mode. The computer system comprises a first portion comprising a graphics processing unit, a memory space and a display; and a second portion comprising a storage storing an image data. When the computer system operates in the image-reading mode, the image data has been transferred to the memory space from the storage, the second portion enters to the second power-management mode from the first power-management mode, and the first portion keeps in the first power-management mode, so that the graphics processing unit can display an image by the display according to the image data stored in the memory space.

Computer system and method for saving power consumption by placing a second computer portion into a sleep mode after completed transfering image data to a first computer portion

A hard drive assessing method and a hard drive assessing system supporting a maximum transmission rate of a hard drive are provided, wherein the hard drive is accessed by a controller, and both the controller and the hard drive support a plurality of transmission rates. The maximum transmission rate of the hard drive is first obtained. When the controller reads data from the hard drive, the transmission rate of the controller is set to be not lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. When the controller writes data into the hard drive, the transmission rate of the controller is reduced to be lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. Thereby, the hard drive can be accessed at its maximum transmission rate.

Hard drive accessing method and hard drive accessing system supporting maximum transmission rate of hard drive

In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.

Method for initializing bus device

A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.

Method for accessing memory data

For saving power of a central processing unit at a Cpower level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the Cpower level. Afterwards, in response to a bus master request, the central processing unit is switched from the Cpower level to a transitional Cpower level while keeping the arbitrator disabled, and then switched from the transitional Cpower level to a Cpower level while enabling the arbitrator to process the bus master request.

Method and system for saving power of central processing unit

A bus cycle trapping system includes at least one register, a north bridge, a south bridge and a central processing unit (CPU). The register is configured to store at least one trapping parameter. The north bridge traps a bus cycle matching the at least one trapping parameter while issuing an activating signal. The south bridge sends a system management interrupt message according to the activating signal. The CPU enters a system management mode according to the system management interrupt and executes a system management interrupt routine for doing a debugging test of the bus cycle matching the trapping parameter.

System and method for trapping bus cycles

A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Power saving method of central processing unit

A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Power saving method and system for a central processing unit disposed in a non-snooping sleep state when a peripheral device sends a bus master request

Apparatus and methods of adjusting system efficiency for a current-consuming system are disclosed. In the disclosed apparatus, a system current detector receives a system current from the current-consuming system and calculates a system current variation accordingly. A system efficiency adjustment module is coupled to the system current detector to receive the system current variation and output a frequency control signal and a voltage control signal accordingly.

Apparatus and method of adjusting system efficiency

An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Interruption control system and method

A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Device for debugging and method thereof

A method and apparatus for driving a non-native SATA hard disk applied in a computer is provided. The computer includes a basic input/output system (BIOS) and an operating system (OS), both of which support an advanced configuration and power interface (ACPI). The non-native SATA hard disk includes a conversion interface and a parallel ATA (PATA) internal disk. First, issue an interrupt. Then, process an interrupt handle routine for detecting and saving the timing mode of the PATA internal disk. Next, load a default IDE driver. Then, report the saved timing mode. Finally, set the SATA hard disk according to the timing mode.

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Taipei, Taiwan

Chung-Ching Huang