National Yang Ming Chiao Tung University

Winbond Electronics Corporation

Chung-Chih Hung

Shih-Hsing Wang

Chung-Yu Wu

Chun-Yu Lin

Yi-An Chen

Xin-Hong Qian

Chun-Yen Chiang

Chia-Fone Lee

Fang-Ting Chou

Fang-Ding Chou

Yuan-Fang Chou

Wen-Hung Hsieh

Ming-Tse Lin

Jia-Heng Chang

A comparator circuit with low power consumption and low kickback noise includes a first dynamic comparator and a second dynamic comparator. The first dynamic comparator is a pre-amplifier for the second dynamic comparator. An enable switch which is connected to the first dynamic comparator has a control terminal connected to a resistance device. The resistance device and the enable switch form a RC delay circuit to reduce the kickback noise of the comparator circuit. Since the comparator circuit is composed of dynamic comparators, the power consumption of the comparator circuit is lower.

Comparator circuit with low power consumption and low kickback noise

A cochlear implant device comprises a receiver, a processing device, a first electrode and a second electrode. The receiver is configured to receive outside voice signal. The processing device is coupled to the receiver, configured to receive and transfer the voice signal to an electrical stimulation signal. The first electrode connects to the processing device, disposed on stapes footplate ligament or oval window. The second electrode connects to the processing device, disposed on round window. Wherein the electrical stimulation signal is applied to stapes footplate ligament, oval window or round window to stimulate acoustic nerve through the first electrode or the second electrode.

Cochlear implant device and stimulating method thereof

A pseudo resistor with tunable resistance including a first transistor and a second transistor is provided. The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor serves as a first terminal of the pseudo resistor. The control terminal of the first transistor receives a control voltage. The first transistor is controlled by the control voltage, such that the first transistor operates in a weak inversion region. The second transistor has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor and the control terminal of the second transistor are coupled to each other to serve as a second terminal of the pseudo resistor with tunable resistance. The second transistor operates in the weak inversion region.

Pseudo resistor with tunable resistance

A two-step switching method of circuit switch can be used in a charge pump circuit of a phase locked loop circuit. In the method, a first type switch and a second type switch which have the same sizes and are opposite in type, are provided. The first type switch and second type switch continuously receive an input current, and the input current is kept at a low current state in a first stage before the first type switch and the second type switch are turned on. In a second stage, the first type switch and the second type switch are turned on, the input current is gradually adjusted to a target current state, and the input current of the target current state is gradually supplied to an external circuit. The present method can reduce noise generated by the external circuit, reduce power loss, and offset charge injection.

Two-step switching method for a circuit switch

A charge pump circuit and a phase-locked loop (PLL) system using the same are provided. The charge pump circuit includes an upper current source, a lower current source and a plurality of switches. The switches are turned on or off by an error signal to increase or decrease the control voltage of the voltage-controlled oscillator (VCO) and further control the frequency of the output signal of the VCO. When the reference frequency signal matches with the divided frequency signal from the VCO, the upper current source and the lower current source are bypassed to decrease the voltage across the MOSFET, thereby minimizes the influence of the leakage current on the control voltage of VCO. In this way, the output jitter can be reduced due to smaller magnitude of peak-to-peak voltage on the control voltage of VCO in the PLL system caused by the leakage current of the MOSFET.

Charge pump circuit and phase locked loop system using the same

A lithium battery control circuit and a lithium battery charger are provided. The lithium battery charger includes the lithium battery control circuit. The lithium battery control circuit includes a smooth transition circuit and an off-time control circuit. The smooth transition circuit generates a first voltage according to a sense current signal and a feedback signal, and generates a second voltage according to a mode signal. The smooth transition circuit compares the first voltage with the second voltage to generate a reset signal. The off-time control circuit converts the feedback signal to generate a first current by a voltage-to-current mechanism, and generates a set signal by using the first current and a duty ratio signal. The invention may prevent a surge current and an oscillation phenomenon by the smooth transition circuit. A switching frequency and a ripple size of an output current are controlled by the off-time control circuit.

Lithium battery control circuit and lithium battery charger with surge current protection

A digital to analog converter is provided, including a buffer circuit, a current switch circuit, and a weighted current generating circuit. The buffer circuit receives an N-bit digital signal and a clock signal, accordingly outputs N switch control signals. The current switch circuit includes N switches which are connected or disconnected according the switch control signals. The weighted current generating circuit includes M current source arrays, where each current source array outputs K output currents. Current values of each output current of each current source array respectively ascend in a binary-weighted manner. A minimum output current of an mth current source array is two times of a maximum output current of a (m&#x2212;1)th current source array, N is obtained by multiplying M by K, and 1&#x2266;m&#x2266;M. An output of the digital to analog converter is a total current value of the output currents outputted by the M current source arrays.

Digital to analog converter for performing digital to analog conversion with current source arrays

A charging structure including a power supply device, a rechargeable battery and a charging management device is provided. The power supply device is configured to provide a system voltage. The charging management device is configured to switch a corresponding charging mode according to the voltage level of the positive end of the rechargeable battery. The charging management device stops charging action when a charging current for charging the rechargeable battery drops down to a pre-set current value.

Charging structure

A digital-to-analog conversion device is disclosed. The digital-to-analog conversion device comprises a variable delay buffer circuit and a plurality of synchronization circuits. The buffer circuit receives a digital signal with a plurality of bits and sequentially outputs a plurality of first complementary digital signal sets delayed according to the order of from MSB to LSB. Each synchronization circuit receives the first complementary digital signal set and a clock signal, uses the clock signal as the timing reference of the first complementary digital signal set, and outputs a second complementary digital signal set corresponding to the first complementary digital signal set to a digital-to-analog conversion unit, so as to convert the second complementary digital signal sets into an analog signal. The present invention uses the delays respectively corresponding to different input bits to control the timing of current switches, whereby the transient glitches are reduced.

Digital-to-analog conversion device

The present invention relates to a digital-to-analog converter comprising a differentiation circuit, a conversion circuit, and an integration circuit. The differentiation circuit receives and differentiates a digital signal for producing a differentiation signal. The conversion circuit is coupled to the differentiation circuit. It receives the differentiation signal and produces a conversion signal according to a clock signal and the differentiation signal. The integration circuit is coupled to the conversion circuit. It receives and integrates the conversion signal for producing an analog signal. Thereby, the purpose of reducing distortion noises can be achieved.

Digital-to-analog converter

A current mode dual-slope temperature-to-digital conversion device is disclosed. The conversion device comprises a temperature dependent current source and a reference current source. Firstly, a capacitor is charged by the temperature dependent current source. Next, the capacitor is discharged by the reference current source. The capacitor is coupled to at least one trigger, and the trigger sends out a first digital signal to a logic controller by the voltage of the capacitor. Then, the logic controller sends out a second digital signal to a time-to-digital converter according to the first digital signal. When the capacitor is discharged by the reference current source and before the first digital signal is varied, the converter receives the second digital signal and a clock signal to generate a corresponding digital output value. The present invention achieves the requirement of the high linearity resolution with the dual-slope architecture lest the curvature effect resulted from the time-domain circuit be occurred.

Growing community of inventors

Tainan County, Taiwan

Chung-Chih Hung