Upbeat Technology Co., Ltd

Ncku Research and Development Foundation

Chung-Chieh Chen

Shuo-Hong Hung

Bing-Chen Wu

Da-Ming Chiang

Soon-Jyh Chang

Hsien-Lung Ho

Kai-Cheng Cheng

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprises: a plurality of switch capacitor arrays, used to sample an analog input signal; a noise shaping circuit including a fourth-order CIFF (Cascade of Integrators with Feed-Forward) loop filter having two second-order cascaded CIFF loop filters, in the fourth-order CIFF loop filter, a first-order extraction capacitor and a second-order extraction capacitor sharing a first amplifier, and a third-order extraction capacitor and a fourth-order extraction capacitor sharing a second amplifier; a comparator for comparing a plurality of output signals from the noise shaping circuit to produce a plurality of comparison results; and a logic circuit for generating a digital output signal and controlling the switch capacitor arrays based on comparison results from the comparator.

High-order noise-shaping successive approximation register (SAR) analog-to-digital converter and method thereof

A static random-access memory (SRAM) circuit and associated read operation method and write operation method are provided. The SRAM circuit includes memory units arranged in M columns and N rows, M bit lines, N row-voltage selection lines, N word lines, and a control circuit. The control circuit includes a controller, a voltage source, a voltage selection module, a word-line driving module, and a bit-line driving module. The voltage source provides a first voltage and a second voltage. When the control circuit performs access to the memory unit located in the mth column and the nth row, the voltage selection module transmits one of the first voltage and the second voltage to an nth row-voltage selection line. The voltage selection module transmits the second voltage to the other (N−1) row-voltage selection lines. The variables M, N, m, and n are positive integers.

Static random access memory circuit and read/write operation method thereof

An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.

Error detection and correction method and circuit

A micro-electro-mechanical system acoustic sensor, a micro-electro-mechanical system package structure and a method for manufacturing the same are provided. The micro-electro-mechanical system acoustic sensor comprises a substrate, a cantilever structure and a diaphragm sensor. The cantilever structure is formed on the substrate, and comprises a fixed end and a free cantilever portion extended from the fixed end. The free cantilever portion comprises a free end. The free end and the fixed end are respectively at opposing sides of the free cantilever portion. The free cantilever portion is capable of generating a vibration wave in an empty space. The diaphragm sensor is formed on the substrate, and comprises a diaphragm film, a back plate, and at least one electrical contact point. The back plate and the diaphragm film have a first empty gap there between. The empty space and the first empty gap communicate to each other.

Growing community of inventors

Taipei, Taiwan

Chung-Chieh Chen