Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Mosel Vitelic Corporation

Integrated Circuit Solution Inc.

Chung-Cheng Wu

Chih-Hao Wang

Ying-Keung Leung

Carlos H Diaz

Zhiqiang Wu

Chun-Hsiung Lin

Ta-Pen Guo

Wen-Hsing Hsieh

Min Cao

Yi-Ming Sheu

Jean-Pierre Colinge

Chia-Hao Chang

Wai-Yi Lien

Hung-Li Chiang

Ming-Tzong Yang

Gwan-Sin Chang

Huan-Sheng Wei

Ching-Wei Tsai

Da-Wen Lin

Hsiang-Jen Tseng

Shyue-Shyh Lin

Chia-Wen Liu

Kuo-An Liu

Zhi-Qiang Wu

Ali Keshavarzi

Yee-Chia Yeo

Bharath Kumar Pulicherla

Kuan-Lun Cheng

Li-Chun Tien

Lee-Chung Lu

Chan-Lon Yang

Tzer-Min Shen

Yung-Chin Hou

Kuo-Cheng Ching

Yen-Ming Chen

Chih Chieh Yeh

Jung-Chan Yang

Chien-Tai Chan

Li-Chun Li

Jon-Hsu Ho

Szu-Wei Huang

Huoy-Jong Wu

Saysamone Pittikoun

Chih-Han Lin

Yu-Ming Lin

Clement Hsingjen Wann

Jiann-Tyng Tzeng

Wen-Ting Chu

Shye-Lin Wu

Chun Hsiung Tsai

Sang Hoo Dhong

Pinyen Lin

Li-Te S Lin

Cheng-Yi Peng

King-Yuen Wong

David Barry Scott

Ken-Ichi Goto

Cheng-Ting Chung

Ting Yu Chen

Chun-Fu Cheng

Ming-Lung Cheng

Hong-Tsz Pan

Ching-Fang Huang

Shyh-Wei Wang

Sheng-Jier Yang

Ching-Hua Lee

Bi-Ling Lin

Cheng-Ku Chen

Yi-Han Wang

Shu-Hui Sung

Carlos Hernando Diaz

Harry-Hak-Lay Chuang

Li-Jui Chen

Yasutoshi Okuno

Pang-Yen Tsai

Chia-Pin Lin

Kuo-Ching Huang

Yi-Hsun Chiu

Yu-Xuan Huang

Shang-Wen Chang

Jenn Ming Huang

Sheng-Kang Yu

Tien-Wei Chiang

Yi-Hsiung Lin

Shui-Hung Chen

Chia-Hsiang Chen

Li-Ping Huang

An-Shen Chang

Yen-Chun Lin

Chih-Hsiang Huang

Cheng-Long Chen

Jyh-Haur Wang

Haiting Wang

Jung-chan Yang

Ting-Yu Chen

Shu-Min Chen

Ji-Chung Huang

Che-Yu Yeh

Li-Wen Weng

A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Contacts for highly scaled transistors

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Integrated circuit structure and method with hybrid orientation for FinFET

A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Semiconductor device and manufacturing method thereof

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Integrated circuits and manufacturing methods thereof

A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Method of fabricating a multi-gate device

Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

Method for manufacturing semiconductor structure

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a &#x3c;100&#x3e; crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a &#x3c;110&#x3e; crystalline direction along the first direction.

A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Multi-gate device

Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction. The fin-like semiconductor layer includes a third semiconductor material that is configured differently than the first semiconductor material.

Horizontal gate all-around device having wrapped-around source and drain

Growing community of inventors

Hsin-Chu County, Taiwan

Chung-Cheng Wu