United Microelectronics Corp.

Chung-Cheng Tsai

Ya-Nan Mou

Hsin-Pang Lu

Shi-Wen Chen

Yu-Tse Kuo

Chun-Yen Tseng

Hsin-Wen Chen

Yuan-Hui Chen

Chih-Wei Tsai

Chi-Chang Shuai

Chung-Hao Chen

Chi-Hsiu Hsu

Hai Thanh Nguyen

Tsan-Tang Chen

Yen-Hsueh Huang

Chang-Ting Lo

Zih-Yu Chiu

An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

Static random access memory

An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

Static random access memory device with keeper circuit

A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

Read only memory

An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N&#x2212;M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N&#x2212;M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Memory and operation method thereof

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Memory for a voltage regulator circuit

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Operation method of a supply voltage generation circuit used for a memory array

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array

A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.

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Taichung, Taiwan

Chung-Cheng Tsai