Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Cheng Chen

Po-Wei Chen

Ming-Sung Kuo

Chien-Li Kuo

Po-Tao Chu

Shen-Ping Wang

Ming-Hong Chang

Hsun-Kuo Hsiao

Hsin-Chih Lin

Fang-yu Liu

Chih-Yuan Chan

Ping-Cheng Ko

Jhih-Yuan Yang

Min-Sung Kuo

I-Kai Hung

A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas:

Method for measuring overlay shift of bonded wafers

Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Semiconductor devices and methods of manufacture

A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wxmeasured along a first axis. The bottom wafer pattern includes a first part with a width Wxmeasured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas:2;1;

Measurement pattern and method for measuring overlay shift of bonded wafers

An apparatus for storing and transporting semiconductor elements includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pin holder integrally extending from the first rear side wall. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pivotal pin structure integrally coupled with and extending from the second rear side wall. The at least one pivotal pin structure comprises a shaft, and a head connected with the shaft. The at least one pin holder defines a cavity sized and shaped to accept the head of the at least one pivotal pin structure. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

Apparatus for storing and transporting semiconductor elements, and method of making the same

A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

Group III-V device structure

Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.

Growing community of inventors

Toufen, Taiwan

Chung-Cheng Chen