United Microelectronics Corp.

Chung-Che Huang

Ping-Chia Shih

Yu-Cheng Wang

Chin-Fu Lin

Chi-Cheng Huang

Chun-Sung Huang

Kuo-Lung Li

Hsiang-Chen Lee

Kun-I Chou

Yu-Chun Chang

Yuan-Cheng Yang

Wan-Fang Chung

Wei-Pin Huang

Chia-Cheng Hsu

Shao-Nung Huang

Che-Hao Chang

Cheng-Chi Tai

Jhih-Long Lin

Chun-Ju Tao

Jaw-Jiun Tu

Mu-Jia Liu

A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H/Nplasma treatment process is performed to reduce the main conductive material.

Semiconductor process for treating metal gate

A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed edge

A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Method for manufacturing semiconductor device

An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Method of etching oxide layer and nitride layer

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Tainan, Taiwan

Chung-Che Huang