Lantiq Deutschland Gmbh

Maxlinear, Inc.

Infineon Technologies Ag

Lantiq Beteiligungs Gmbh & Co. Kg

Chunfeng Hu

Ingo Volkening

Shridhar Mubaraq Mishra

Rajan Raghvendra

Hak Keong Sim

Tina Zhang

Bernd Heise

Dietmar Schoppmeier

Gert Schedelbeck

Michael Horvat

Jiaxiang Shi

Jia Xiang Shi

Juraj Povazanec

Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

Adaptive clock signal frequency scaling

A system includes an internal memory configured to store data, a memory access controller, logic, and a processor. The memory access controller is operable to read data from a peripheral device in response to an event external to the system, write the data to memory external to the system and forward the data or a portion of the data to the internal memory. The logic is operable to track which portion of the data is stored in both the external memory and the internal memory. The processor has one or more caches logically and physically separated from the internal memory. The processor is operable to retrieve the data forwarded to the internal memory and use the retrieved data to begin servicing the event.

System with internal memory for storing data or a portion of data written to external memory

Embodiments related to retransmission and a retransmission request are described and depicted.

Retransmission and retransmission request in data communication systems

An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.

Configurable fast ethernet and gigabit ethernet data port

Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.

High speed memory access in an embedded system

An encapsulation apparatus for encapsulating data includes an input to receive the data, a machine to generate information related to the encapsulation of data and a logic coupled to the machine. A processing machine is coupled to the input and the logic.

Encapsulation of data

An Ethernet switch has at least one ingress/egress portwhich is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaceseach of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit moduleswhich receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.

There is provided an apparatus and method for ATM bonding. The apparatus comprises a first unit having a first xDSL line connected thereto, a second unit having a second xDSL line connected thereto and a connection between the first unit and the second unit. The first unit is arranged to convert one incoming ATM datastream to a plurality of data and to convert a plurality of incoming data to one ATM data stream. The first unit is arranged to implement the ATM bonding layer of the ATM protocol. The second unit may be arranged to implement one or more of the higher layers. The method comprises the steps of: a first unit receiving an ATM data stream; the first unit converting the ATM data stream into a plurality of data; the first unit transmitting a first one of the plurality of data over a first xDSL line connected to the first unit; the first unit sending a second one of the plurality of data to a second unit via a connection; and the second unit transmitting the second one of the plurality of data over a second xDSL line connected to the second unit.

ATM bonding

A parser system is arranged to receive a data stream () having interleaved sections derived from a plurality of different packets, and to extract data from each section as it arrives. The parser system has a scanning section which receives information about each of the sections of data defining which packet it relates to, and employs this information and the properties of the data stream, to identify the locations of layer (), layer () and layer () data. This information is passed to parser units (), () which extract data based on this data and also offsets. The offsets for the parser () are stored in user-programmable registers ().

Growing community of inventors

Singapore, Singapore

Chunfeng Hu