Pmc-sierra Us, Inc.

Microsemi Solutions (us), Inc.

Chunfang Xie

Bruce Scatchard

Kenneth David Wagner

Scott Barrick

Peter Onufryk

A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.

Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits

A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that substantially increases the V(threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The semiconductor process technique is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for unused circuits having previously applied semiconductor process techniques, such as a high Vcircuit, a standard Vcircuit, a low Vcircuit, and an SRAM cell Vcircuit.

Method of reducing current leakage in a product variant of a semiconductor device

A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the V(threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vcircuit, a standard Vcircuit, a low Vcircuit, and an SRAM cell Vcircuit.

Growing community of inventors

Coquitlam, Canada

Chunfang Xie