Agere Systems Inc.

Chunbing Guo

Fuji Yang

Kameran Azadet

Jinghong Chen

Fadi Saibi

The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals.

Duty cycle correction circuit for high-speed clock signals

Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase comparator to lock the VCO to a reference signal. In addition to frequency divider outputs for use as subcarriers, e.g., binary division factors of the VCO frequency, a quadrature mixer multiplies and adds corresponding quadrature components at two of the frequencies, to generate a differential signal at a difference frequency. The mixer may be outside of the feedback signal path but preferably is in the feedback path to suppress noise. A polyphase filter converts the mixer output to a quadrature signal useful as a subcarrier. The technique efficiently generates sequential integer multiples of a basic frequency, such as sixteen adjacent integer multiples of a frequency reference.

Multiple frequency generator for quadrature amplitude modulated communications

A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

Common-mode shifting circuit for CML buffers

A method and apparatus are provided for detecting a receiver over a PCI-Express bus. A receiver is detected on a PCI-Express link by adjusting a common mode voltage using a current injected into one or more transmitter output nodes and detecting whether a receiver is present based on a voltage change rate. The current can be injected, for example, by a charge pump. In various embodiments, the charge pump can be integrated with a CML transmit buffer or an H-bridge type of transmit buffer. The amplitude control circuit can compare the adjusted common mode voltage to one or more predefined voltages and maintain the adjusted common mode voltage between two predefined voltages. The amplitude control circuit provides a signal to the charge pump to control the current injected into the transmitter output nodes. The amplitude control circuit also provides a signal to an exemplary timer that measures the voltage change rate.

Method and apparatus for receiver detection on a PCI-Express bus

A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N&#x2266;T.

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Eatontown, NJ, United States of America

Chunbing Guo