Via Technologies, Inc.

Chun-Yuan Su

Jiin Lai

Chau-Chad Tsai

Chi-Che Tsai

I-Lin Hsieh

Chi-Feng Lin

Wen-Hao Chuang

A system for a first device to initialize a second device is disclosed. The initialization bus is coupled between the first device and the second device. During an initialization period, the first device triggers at least one transmission command through the initialization bus to transmit at least one initial value to the second device via the initialization bus.

Method and system for initializing devices

In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a certain sub data is received, the corresponding bit of the enable bit array is enabled. The corresponding sub data of the enabled bit is indicated by the address pointer.

Data buffering method

A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of the data region is updated. Finally, the count value and a value of maximum data length are compared to determine whether to increase the number of the packets that can be stored in the buffer.

Buffer control method and device thereof

A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.

Chipset and northbridge with raid access

System and related method for testing a chip with a high-speed bus interface in a low speed testing environment is provided. The testing method for testing input/output functions of a chip includes: establishing an inner loop path between a transmission mechanism and a receiving mechanism of the chip; transmitting a testing data; and receive the testing data via the inner loop path.

System and related method for chip I/O test

An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

Expansion adapter supporting both PCI and AGP device functions

A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

Growing community of inventors

Taipei, Taiwan

Chun-Yuan Su