Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Shuttle Inc.

Chun-Yuan Chou

Da-Yuan Lee

Kuang-Yuan Hsu

Xiong-Fei Yu

Jeff J Xu

Chung-Chiang Wu

Chia-Ching Lee

Jian-Hao Chen

Peng-Soon Lim

Cheng-Hao Hou

Fan-Yi Hsu

Hsueh-Wen Tsau

Ming-Hsing Tsai

Cheng-Yen Tsai

Weng Chang

Ching-Hwanq Su

Ching-Ray Chang

Po-Cheng Kuo

An-Cheng Sun

Fun-Son Yeh

Yen-Hsiang Fang

Tao-Hsuan Yang

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Techniques providing metal gate devices with multiple barrier layers

A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.

Semiconductor structure

Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.

Structure and formation method of semiconductor device structure

A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.

Semiconductor structure and methods of forming the same

A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.

Semiconductor device and manufacturing method thereof

An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of HO, NHOH, HCl, HSOor diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NHOH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.

Method of forming metal gate electrode

A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.

Metal gate electrode of a field effect transistor

An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.

A novel heat assisted magnetic recording (HAMR) medium and the fabrication method therefor are provided. The exchange coupling effect occurring at the interface of FePt/CoTb double layers is adopted, and thus the resulting magnetic flux would be sufficient enough to be detected and readout under the room temperature. The provided HAMR medium exhibits a relatively high saturation magnetization and perpendicular coercivity, and thus possesses a great potential for the ultra-high density recording application.

Heat assisted magnetic recording medium and method for fabricating the same

An active start judgment circuit is electrically connected to an AC/DC transforming power supply which has at least one standby power unit to transform AC to DC in regular conditions and a main power unit to transform the AC to the DC in an ON condition for operation of an electronic equipment. The start judgment circuit bridges the standby power unit and the main power unit, and generates a reference potential based on a voltage output from the standby power unit, and gets a power signal from the standby power unit to be compared with the reference potential to output a start signal to the main power unit to transform the AC to the DC. Thus the standby power unit can actively drive the main power unit to supply DC power to activate the electronic equipment.

Growing community of inventors

Taipei, Taiwan

Chun-Yuan Chou