Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Industrial Technology Research Institute

Epistar Corporation

Chun-Yuan Chen

Huan-Chieh Su

Chih-Hao Wang

Cheng-Chi Chuang

Li-Zhen Yu

Yen-Ting Chiang

Dun-Nian Yaung

Ching-Chun Wang

Hsiao-Hui Tseng

Yu-Ming Lin

Jen-Cheng Liu

Shyh-Fann Ting

Wei Chuang Wu

Shih-Chuan Chiu

Jhy-Jyi Sze

Pei-Yu Wang

Chia-Hao Chang

Lo-Heng Chang

Yu-Jen Wang

Kuan-Lun Cheng

Feng-Chi Hung

Yi-Hsun Chiu

Ching-Wei Tsai

Tien-Lu Lin

Jia-Chuan You

Tzu-Jui Wang

Lin-Yu Huang

Yuichiro Yamashita

Shen-Hui Hong

Lu-Sheng Chou

Hsuan-Han Tseng

Ming-Hsien Yang

Yen-Yu Chen

Keng-Yu Chou

Yu-Xuan Huang

Shang-Wen Chang

Sheng-Chan Li

Yi-Bo Liao

Han-Ping Kuo

Chia-Hao Wu

Chia Ching Liao

Jiann-Tyng Tzeng

Wei-Cheng Lin

Chih-Wei Chen

Sheng-Tsung Wang

Wei-An Lai

Ching I Li

Kai-Yun Yang

Wei-Chuang Wu

Hsu-Sheng Hsu

Chih-Chun Chang

Ming Chian Tsai

Kuan-Tsun Chen

Kuo-Cheng Chiang

Kuo-Nan Yang

Hou-Yu Chen

Chih-Ming Wang

Ru-Shi Liu

Shun-Nan Liou

Ming-Jye Tsai

Hao-Yu Chen

Yih-Hua Renn

Shau-Yu Tsai

Chih-Kang Wu

Po-Lung Chen

Hou-yu Chen

Chih-Wei Chien

Hui-Kai Chou

Chien-Chun Kuo

Chih-Ling Hsueh

I-Lun Ma

Yung-Hsiang Lin

Chih-Kai Chiu

Jr-Wei Lian

Min-Hsuan Lu

Shu-Fen Hu

Yin-Ting Lee

Kai-Shiang Gan

Shih-Wei Hsieh

Yung-Wen Hsu

Hao-Yuan Hou

Chien-Hsin Wang

Chang-Tai Hisao

A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.

Semiconductor structure with contact rail and method for forming the same

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.

Semiconductor device including spacers on sides of dielectric structure and manufacturing method thereof

In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Vertical gate field effect transistor

A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

High capacitance MIM device with self aligned spacer

A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Semiconductor device with backside power rail

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.

Full well capacity for image sensor

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Semiconductor device structure and method for forming the same

The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Semiconductor devices with backside power rail and methods of fabrication thereof

A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Semiconductor device having dielectric hybrid fin

A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.

Method for forming semiconductor device

A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Semiconductor device and method of manufacturing the same

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Backside gate contact

A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Semiconductor device with backside gate isolation structure and method for forming the same

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Hsinchu, Taiwan

Chun-Yuan Chen