Macronix International Co., Ltd.

Grain Electronics, Inc.

Chun-Yu Liao

Ken-Hui Chen

Su-Chueh Lo

Shang-Chi Yang

Kuen-Long Chang

Chia-Jung Chen

Shih-Chang Huang

Ti-Wen Chen

Fu-Nian Liang

Tzung-Shen Chen

Yung-Hsu Chen

Lu-Chia Liao

Chun-Chun Liao

Yi-Wei Chang

An intelligent display assembly includes a display and a microcontroller. The display is mounted to a CNC machine and provided with a light emitting module and a display module opposite to the light emitting module. The microcontroller is electrically connected with the CNC machine and the display, such that the microcontroller receives an operating status signal outputted by the CNC machine, and according to the operating status signal, the microcontroller controls the light emitting module to emit light and controls the display module to display processing information, such as processing time, processing quantity, waiting time, and failure time. This allows operators to grasp the processing information in real time and improve management efficiency.

Intelligent display assembly for CNC machine

The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

Memory device and method for operating the same

Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.

Memory device and operation method thereof

A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.

Circuit and method for read latency control

A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.

Leakage compensation read method for memory device

A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

Memory and method for operating a memory with interruptible command sequence

A row decoder includes a plurality of address lines, a first selection circuit and a second selection circuit. The first selection circuit is coupled to the address lines and with a latch function, and configured to enable and latch a first selection signal to select a first word line in a first cell array. The second selection circuit is coupled to the address lines and without the latch function, and configured to enable a second selection signal to select a second word line in a second cell array.

Row decoder and memory system using the same

A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor.

Local word line driver of a memory

An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step.

Operation method and leakage controller for a memory and a memory applying the same

A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt level of a second-side of the target cell and accordingly obtaining a corrected PV level corresponding to the first-side; and programming the first-side of the target cell to have a Vt level not lower than the corresponding corrected PV level.

Method for reading and programming a charge-trap memory device compensated for an array/second-bit/neighbor-bit effect

A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.

Memory circuit with high reading speed and low switching noise

A method for programming a memory is provided. The memory includes multiple rows of memory cells each including two half cells. The method includes the following steps. Whether the two half cells of a to-be-programmed memory cell of the nrow memory cells are both needed to be programmed or not is determined, wherein n is a positive integer. If the two half cells of the to-be-programmed memory cell are both needed to be programmed, a first initial programming bias voltage corresponding to the nrow memory cells is applied to program the to-be-programmed memory cell. Otherwise, a second initial programming bias voltage corresponding to the nrow memory cells is applied to program the to-be-programmed memory cell. The second initial programming bias voltage is higher than the first initial programming bias voltage.

Memory and method for programming the same

A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 2bits is received. Next, an error correction code, a parity code and a data code are generated and written in the memory. Then, the at least one piece of data fragment is read from the memory and used as at least one piece of read data fragment. Next, a new error correction code, a new parity code and a new data code are generated. Afterwards, a determination as to whether the at least one piece of read data fragment has a 1-bit error is made. After that, if the at least one piece of read data fragment does not have a 1-bit error, then the at least one piece of read data fragment is outputted.

Memory and 1-bit error checking method thereof

A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

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Taichung, Taiwan

Chun-Yu Liao