Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming Chi University of Technology

Tsinghua University

Chun-Ying Lee

Yih Wang

Tung-Cheng Chang

Chia-En Huang

Gu-Huan Li

Chieh Lee

Perng-Fei Yuh

Kun-Cheng Peng

Yi-Ching Liu

Chia-en Huang

Meng-Sheng Chang

Meng-Fan Chang

Jonathan Tsung-Yung Chang

Yao-Jen Yang

Kuan-Chung Chiu

Chi-Ting Chung

Po-Yan Su

Kuan-Ting Wu

Ruei-You Liou

Chen-Wei Chu

Yi-Xian Li

Yan-Chen Lin

Wei-Hua Chen

Rose Tseng

Min-Zen Lee

Yao-Tien Tseng

An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the first direction; and a fourth n-channel layer engaged with a fourth gate layer to form a sixth device, the fourth gate layer coupled to a second word line and the fourth n-channel layer coupled to the third n-channel layer along the second direction.

Structures of sram cell and methods of fabricating the same

A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.

Semiconductor device with a vertical channel wrapped around gate, and method for manufacturing the same

A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

Memory device with reduced area

A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Memory device and operating method of the same

A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Semiconductor memory devices with diode-connected MOS

A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Memory array connections

A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Memory circuits and devices, and methods thereof

A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

Memory array circuits, memory structures, and methods for fabricating a memory array circuit

A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

The manufacturing method of titanium dioxide solution includes: mixing choline chloride, urea, boric acid, and titanium tetrachloride to form a first solution, wherein a molar concentration ratio of choline chloride to urea is 1:2, a molar concentration of titanium tetrachloride is 0.2 M to 0.4 M, and weight/volume of boric acid is 5 g/300 ml to 15 g/300 ml; and heating the first solute ion to form a second solution, wherein the second solution contains carbon/nitrogen doped titanium dioxide. In the manufacturing method of the present disclosure, the deep eutectic solution formed by choline chloride and urea may be used as a solvent, and may also be used as a carbon source and/or a nitrogen source. Therefore, titanium dioxide may be doped with carbon and/or nitrogen during the formation process.

Manufacturing method of titanium dioxide solution and titanium dioxide film

The present disclosure provides a manufacturing method of indium tin oxide, including: providing a first electrolyte including choline chloride, urea, indium chloride, boric acid, and ascorbic acid; disposing a workpiece, wherein at least a part of the workpiece is in contact with the first electrolyte; heating the first electrolyte to 60&#xb0; C.-95&#xb0; C.; applying a first operating current to electroplate indium onto the workpiece; providing an second electrolyte including choline chloride, urea, tin chloride, boric acid, and ascorbic acid; disposing the indium-coated workpiece, wherein at least a part of the workpiece is in contact with the second electroplate; heating the second electroplate to 60&#xb0; C.-95&#xb0; C.; applying a second operating current to electroplate tin onto the workpiece; and annealing the indium and tin on the workpiece to form indium tin oxide in an oxygen environment.

Manufacturing method of indium tin oxide

A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle.

Growing community of inventors

Taipei, Taiwan

Chun-Ying Lee