Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Other

Chun-Ying Chen

Pieter Vorenkamp

Sumant Ranganathan

Neil Y Kim

Young J Shin

Myles H Wakayama

Massimo Brandolini

Tao Wang

Michael Q Le

Andrew J Castellano

Jiangfeng Wu

Ralph A Duncan

Hsiang-Bin Lee

Lawrence M Burns

Agnes Woo

Frank Carr

Lin He

Alexandre Rudolph Kral

Afshin Mellati

Dana Vincent Laub

Tianwei Li

Mo Maggie Zhang

Patrick Pai

Luke Thomas Steigerwald

Wei-Ta Shih

Ramon Alejandro Gomez

Loke Kun Tan

Xicheng Jiang

Kevin Lee Miller

Robert G Wiley

James Y C Chang

Yee Ling Cheung

David S P Ho

Iconomos A Koullias

Pin-En Su

Ron Lipka

Joel I Danzig

Jungwoo Song

Randall Bret Perlow

Hui Pan

Takayuki Hayashi

Kwang Young Kim

Binning Chen

Giuseppe Cusmai

Rong Wu

Chia-Jen Hsu

Wei-Te Chou

Wenbo Liu

Wynstan Tong

Wei Li

Zen-Che Lo

Karthik Raviprakash

Acer Chou

Beth Wilcher

Hemasundar Mohan Geddada

Ayaskant Shrivastava

David SP Ho

James YC Chang

Young Joon Shin

A method and apparatus for calibrating a pipelined analog-to-digital converter (ADC) is disclosed. A method includes reading a first output level from a first sub-ADC, reading one or more additional output levels from one or more additional sub-ADCs, combining the one or more additional output levels from the one or more additional sub-ADCs into a combined output level, and adjusting a comparator threshold of the first sub-ADC when the first output level and the combined output level meet a set of predetermined conditions.

Pipelined analog-to-digital converter calibration

A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.

Digital calibration of capacitive mismatches in analog-to-digital converters

Systems and methods relate to providing a transmit signal. The transmit signal can be provided in a transmitter circuit including a main pre-equalizer, a main power amplifier in communication with the main pre-equalizer, a replica pre-equalizer, and a replica power amplifier in communication with the replica pre-equalizer. The replica preamplifier is in communication with the main pre-equalizer, and control signals are provided to the main pre-equalizer to reduce distortion. The control signals are provided in response to an output signal of the replica power amplifier.

System for and method of reducing transmit signal distortion

The present disclosure is directed to a system and method for adjusting a conversion speed of an asynchronous SAR ADC based on a margin of time between when a conversion of a sample of an analog signal completes and a next sample of the analog signal is taken, referred to as a 'conversion time margin.' The system and method reduce the conversion speed of an asynchronous SAR ADC when the conversion time margin permits to reduce the amount of power consumed and/or noise produced by the asynchronous SAR ADC.

Adaptive asynchronous SAR ADC

The present disclosure provides for an analog-to-digital converter (ADC) which selectively compresses an analog input signal to improve noise performance and dynamic input range. The ADC selectively scales an analog input signal when it is closer to an expected value of one or more signal metrics more than when it is further from the expected value of the one or more signal metrics. For example, during the conversion process, the ADC amplifies the analog input signal when it is closer to a mean value &#x3bc; by a gain factor while selectively adjusting the gain factor when the analog input signal is further from its mean value &#x3bc; to selectively compress the analog input signal. This selective compression improves input noise performance and dynamic input range of the ADC when compared to the conventional ADC.

Companding M-digital-to-analog converter (DAC) for a pipelined analog-to-digital converter (ADC)

A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

System and method for integration of hybrid pipeline

A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.

Time-interleaved skew reduced pipelined analog to digital converter

A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Pipelined analog-to-digital converter with dedicated clock cycle for quantization

Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

Successive equalizer for analog-to-digital converter (ADC) error correction

According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.

System including adaptive power rails and related method

A system and method for providing multi-tiered power save operation in a portable communication device. A portable communication device may be operated in a first power-save mode. A power-save module of the portable communication device may, for example, provide for operation in such a first power-save mode. It may be determined to operate the portable communication device in a second power-save mode that is different than the first power-save mode. A power-save management module may, for example, make such a determination. The portable communication device may then be operated in the second power-save mode. The power-save module may, for example, provide for operation in such a second power-save mode.

Portable communication device with multi-tiered power save operation

Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.

Inter-device adaptable interfacing clock skewing

A system and method for storing power utilization information in an integrated circuit and utilizing such information. Various aspects of the present invention provide an integrated circuit that comprises a first module, which stores power utilization information for at least a portion of the integrated circuit. A second module of the integrated circuit may communicate the power utilization information with an electrical device external to the integrated circuit. Various aspects of the present invention provide a method for storing power utilization information in an integrated circuit. For example, a performance characteristic and/or a power supply characteristic may be monitored as the integrated circuit is utilized. Power utilization information may be determined from the monitored characteristic(s), and the power utilization information may be stored in the integrated circuit. Various aspects of the present invention also provide a system and method for utilizing an integrated circuit having on-board power utilization information.

Integrated circuit with on-board power utilization information

A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator ('VCO'), and a feedback path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator.

Phase-interpolator based PLL frequency synthesizer

A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.

Power control bus

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Irvine, CA, United States of America

Chun-Ying Chen