Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Other

Anaglobe Technology, Inc.

Chun-Yi Yang

Po-Tao Chu

Kun-Ming Huang

Shen-Ping Wang

Chien-Li Kuo

Ming-Hong Chang

Tsai-Feng Yang

Chun-Jung Lin

Chih-Heng Shen

Chan-Hong Chern

Yao-Wen Chang

Kun-Lung Chen

Mam-Tsung Wang

Jiun-Ren Lai

Shi-Xian Chen

Jui-Chin Chang

Ruo-Rung Huang

Yu-Ann Lai

Gwen Chang

Tai-I Yang

Chih-Hao Lin

Tso-Hung Fan

Hong-Seng Shue

Ta-Hung Yang

Yen-Hung Yeh

Yu-Chieh Chou

Lieh-Chuan Chen

Ruei-Hung Jang

Shui-Chin Huang

Ful-Long Ni

Chih-Che Lin

Tsung-Yi Chou

Hsiang-Pang Lee

Shang-Ping Lin

Bing-Ying Wang

Chun-Han Chiang

Ping-Ying Wang

Fu-Yu Chuang

Bo-Qiao Lin

Ting-Chou Lin

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Passivation scheme for pad openings and trenches

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

GaN reliability built-in self test (BIST) apparatus and method for qualifying dynamic on-state resistance degradation

The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.

Method for forming fuse pad and bond pad of integrated circuit

The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.

Ultra high voltage semiconductor device with electrostatic discharge capabilities

A method of redistribution layer routing for 2.5D integrated circuit packages is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a MMSIM (modulus-based matrix splitting iteration method) based routing to assign pre-assignment nets to tracks such that total vertical distance from each bump pair to the assigned track is minimized; and performing a MWMCBM (minimum weighted maximum cardinality bipartite matching) based routing for bumps connected to the assigned tracks according to matching result to complete redistribution layer routing for integrated circuit packages.

Method of redistribution layer routing for 2.5-dimensional integrated circuit packages

A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.

A method for redistribution layer routing is proposed. The method at least comprises inputting information regarding a redistribution layer layout, at least one netlist, and a constraint file. Next, it is creating a concentric-circle model based on the information, the netlist and the constraint file. Subsequently, it is assigning at least one pre-assignment net to at least one redistribution layer according to the concentric-circle model. Finally, the redistribution layer routing is performed.

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages

A method includes forming a drain region in a first layer on a semiconductor substrate. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion are formed having a same doping type and a different doping concentration than the drain rectangular portion.

A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the semiconductor device. The isolating structure has a roughness surface at a sidewall of the isolating structure, and the roughness surface includes carbon atoms thereon.

Isolation structure for semiconductor device

A semiconductor device comprises a semiconductor substrate, a first layer over the semiconductor substrate, and a drain region in the first layer. The drain region comprises a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion have a same doping type and a different doping concentration than the drain rectangular portion.

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Hsinchu, Taiwan

Chun-Yi Yang