Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Yi Shih

Shun-Liang Hsu

Mong-Song Liang

Jyh-Kang Ting

Jin-Yuan Lee

Julie Huang

A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening. The first polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and wherein a portion of a TEOS spacer overlying the buried contact junction is exposed and wherein a portion of the first polysilicon layer other than that of the contact remains as residue. The first polysilicon layer residue is etched away wherein the exposed TEOS spacer protects the buried contact junction within the semiconductor substrate from the etching completing the formation of a buried contact in the fabrication of an integrated circuit.

Method of making buried contact in DRAM technology

A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.

Method of forming a tungsten silicide capacitor having a high breakdown

A new method of forming an improved buried contact junction is described. A first polysilicon layer is deposited overlying a gate silicon oxide layer on the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away where they are not covered by a buried contact mask to provide an opening to the semiconductor substrate. Ions are implanted through the opening into the semiconductor substrate to form a buried contact junction. A layer of dielectric material is deposited over the first polysilicon layer and over the semiconductor substrate within the opening. The layer is anisotropically etched to leave spacers on the sidewalls of the first polysilicon layer and adjacent the opening. A second layer of polysilicon is deposited overlying the first polysilicon layer and over the substrate within the opening. The second polysilicon layer is patterned to form gate electrodes and a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and a portion of a spacer overlying the buried contact junction is exposed and wherein a portion of the second polysilicon layer other than that of the contact remains as residue. The second polysilicon layer residue is etched away wherein the exposed spacer protects the buried contact junction within the semiconductor substrate from the etching to complete the formation of a buried contact in the fabrication of an integrated circuit.

Method of eliminating buried contact trench in SRAM technology

A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.

Method of making high precision w-polycide-to-poly capacitors in

A novel technique for the real time monitoring of ion implant doses has been invented. This is the first real-time monitor to cover the high dosage range (10E13 to 10E16 ions/sq. cm.). The underlying principle of this new technique is the increase in the resistance of a metal silicide film after ion implantation. Measurement of this increase in a silicide film that has been included in a standard production wafer provides an index for correlation with the implanted ion dose.

Growing community of inventors

Hsinchu, Taiwan

Chun-Yi Shih