United Microelectronics Corp.

National Yang Ming Chiao Tung University

Taipei Veterans General Hospital

Chun-Yi Lin

Tzu-Hsuan Huang

Wei-Kai Lee

Hsien-Ta Chung

Cheng-Chia Lee

Yu-Te Wu

Huai-Che Yang

Chu-Ming Ma

Chia-Feng Lu

Chien-Chou Hung

Hung-Chi Huang

Chih-Chun Wu

Wan-Yuo Guo

Wen-Yuh Chung

Hua-Chou Tseng

Cheng-Wen Fan

Shang-Yu Liu

Chih-Yueh Lin

Jie-Ru Bai

Chia-Hong Chin

Cheng-Choug Hung

A method of extracting parasitic parameters of a 3D IC is provided in the present invention, including steps of providing a 3D IC having multiple dies, merging respective layouts of the multiple dies into a common layout, creating a common LVS file and a common LPE file for those multiple dies based on the common layout, creating respective LVS files and respective LPE files for every die based on the respective layouts, creating a common netlist from the common LVS file and common LPE file, creating corresponding respective netlists from the respective LVS files and respective LPE files, merging the common netlist and respective netlists into a netlist, and extracting common parasitic parameters of the dies from the netlist.

Computer readable recording medium with stored program and method of extracting parasitic parameters of a 3D IC thereof

A method for enhancing an accuracy of a benign tumor development trend assessment system includes: a first processing procedure, an image captured before the treatment is inputted to and be processed by a server computing device of the benign tumor development trend assessment system to obtain a first processing result; a second processing procedure, the images captured before and in at least one period after the treatment are inputted to and processed by the server computing device to obtain a second processing result; a trend analyzing procedure, the trend analyzing module of the server computing device analyzes the first processing result, the second processing result and the trend pathways to obtain a tumor development trend result; and a storing procedure, the first processing result, the second processing result and the tumor development trend result are transformed to an individual trend pathway which is stored in the trend analyzing module.

Method for enhancing an accuracy of a benign tumor development trend assessment system

A benign tumor development trend assessment system includes an image outputting device and a server computing device. The image outputting device outputs first/second images captured from the same position in a benign tumor. The server computing device includes an image receiving module, an image pre-processing module, a target extracting module, a feature extracting module and a trend analyzing module. The image receiving module receives the first/second images. The image pre-processing module pre-processes the first/second images to obtain first/second local images. The target extracting module automatically detects and delineates tumor regions from the first/second local images to obtain first/second region of interest (ROI) images. The feature extracting module automatically identifies the first/second ROI images to obtain at least one first/second features. The trend analyzing module analyzes the first/second features to obtain a tumor development trend result.

Benign tumor development trend assessment system, server computing device thereof and computer readable storage medium

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first doped region, a second doped region, a first dielectric layer, a third doped region, a fourth doped region, a second dielectric layer and a conductive layer. The substrate has a first trench in a first area and a second trench in a second area. The first and second doped regions are disposed in the substrate respectively at two side of the first trench. The first dielectric layer is disposed on the sidewall of the first trench. The third doped region is disposed around the second trench. The fourth doped region is disposed in the third doped region at one side of the second trench. The second dielectric layer is disposed on the sidewall and bottom of the second trench. The conductive layer is disposed in the first and second trenches.

Semiconductor device and manufacturing method thereof

The present invention provides a method for improving gate coupling ratio of a flash memory device and a protruding floating gate is formed. First, a substrate having a plurality of isolation structures is formed. Then, a first conductive layer is formed overlaying the substrate. A chemical-mechanical polishing process is performed to planarize the first conductive layer. After that, a portion of the isolation structures is removed, and a second conductive layer is formed overlaying the first conductive layer and the isolation structures. Finally, a lithography process with a photomask can be used to define a mask that covers the first conductive layer and the second conductive layer, and then an insulating layer is deposited overlaying the substrate, so that a third conductive layer is formed overlaying the insulating layer.

Method of fabricating semiconductor structure

A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor opening is formed on the first dielectric layer, in which the capacitor opening is situated directly above the first damascene conductor. Next, an MIM capacitor having a top plate and a bottom plate is created within the capacitor opening, in which the bottom plate of the MIM capacitor is electrically connected to the first damascene conductor. Next, a third dielectric layer is deposited on the second dielectric layer and the MIM capacitor, and at least one second damascene conductor is formed within part of the third dielectric layer, in which the second damascene conductor is electrically connected to the top plate of the MIM capacitor.

MIM capacitor structure and fabricating method thereof

A method for forming a SiGe HBT, which combines a SEG and Non-SEG growth, is disclosed. The SiGe base layer is deposited by a Non-SEG method. Then, the first-emitter layer is developed directly upon the SiGe base layer that has a good interface quality between the base-emitter. Next, a second poly silicon layer, which has a dopant concentration range within 1E19 to 1E21 (atom/cc), is deposited by SEG method. It not only reduces the resistance of the SiGe base layer, but also avoids the annealing that may influence the performance of the device.

Formation method of SiGe HBT

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Hualien County, Taiwan

Chun-Yi Lin