Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

M2 Communication Inc.

Other

United Microelectronics Corp.

Tsinghua University

Elite Semiconductor Microelectronics Technology Inc.

Chun-Yi Lee

Kuen-Long Chang

Chun-Hsiung Hung

Tsung-Chieh Tsai

Juing-Yi Wu

Liang-Yao Lee

Yen-Ming Chen

Kong-Beng Thei

Ping-Wei Wang

Ken-Hui Chen

Jui-Yao Lai

Shyh-Wei Wang

Ming-Hsi Yeh

Harry Chuang

Yung-Feng Lin

Jyh-Kang Ting

Ru-Gun Liu

Tung-Heng Hsieh

Hung-Chang Hsieh

Feng-Jia Shiu

Yi-Ming Sheu

Tsung-Hsing Yu

Yu-Hsien Lin

Chia-Hui Lin

Chun Hsiung Hung

Shin-Jiun Kuang

Chuan-Ying Yu

Hong-Hsien Ke

Yu-Lan Kuo

Wu-Chin Peng

Derrick Wei

Hung-Ta Tso

Chin-Hsiang Lin

Harry-Hak-Lay Chuang

Chi-Ming Yang

Tai-Chun Huang

Yu-Ren Wang

Chii-Ming M Wu

Yung-Chang Chang

Chung-Ting Ko

Jr-Hung Li

Victor Y Lu

Huai-Ying Huang

Chun-Chieh Huang

Neng-Hui Yang

Chia-Wen Liu

Ting-Gang Chen

Yi-Fan Chang

Ming-Chin Tsai

Chieh-Ping Wang

Jenn-Chang Hwang

Yu-Kun Chen

Chih-Ming Chao

Cheng-Lun Tsai

Chin-An Chen

Pei-Tzu Wu

Kuan-Ming Lu

Kuo-Hsi Huang

Liang-Yu Yeh

Meng-Yin Tsai

Yang-Wen Chen

Chia-Chi Hu

Yong-Ling Zhang

Ke-Shiu Chen

Feng-Jui Hu

Li-Shiuan Tsai

Tung-hsiung Liu

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first contact and a second contact disposed over a substrate. A center of a first upper surface of the first contact is laterally separated from a center of a second upper surface of the second contact by a first distance. A first interconnect contacts the first upper surface and a second interconnect contacts the second upper surface. A center of a first lower surface of the first interconnect is laterally separated from a center of a second lower surface of the second interconnect by a second distance that is greater than the first distance.

Different scaling ratio in FEOL / MOL/ BEOL

In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.

Semiconductor device, method, and tool of manufacture

An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Semiconductor device and method of manufacture

An electronic device is capable of determining a radio communications configuration. The electronic device includes a GPS module arranged for receiving an updated GPS coordinate. A controller is electronically coupled to the GPS module, and arranged for controlling the GPS module to receive the updated GPS coordinate and for determining the radio communications configuration based on the updated GPS coordinate received from the GPS module. A transmitter is electronically coupled to the controller and arranged for transmitting a message from the controller according to the determined radio communications configuration.

Electronic device capable of determining low power wide area network communication configuration and method thereof

A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

Cut metal gate devices and processes

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.

Different scaling ratio in FEOL/ MOL/ BEOL

A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.

Mask optimization for multi-layer contacts

An oscillator module used with a plurality of power sources includes an oscillator unit, a clock monitor unit (CMU), a software module and a digital calibration circuit. The oscillator unit generates a clock signal. The CMU is coupled to the oscillator unit, determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if the amplitude of the clock signal is lower than the predetermined threshold. The software module is coupled to the CMU, and receives the alarm signal to output a calibration signal. The digital calibration circuit is coupled to the oscillator and the software module, and outputs a control signal in response to the clock signal and the calibration signal, adjusting the plurality of power sources to modify the clock signal.

Method of monitoring clock and oscillator module thereof

A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Semiconductor device and method for forming same

A power circuit includes a first regulator and an impedance adjustment unit. The first regulator has a loop-back impedance, and provides a first power signal. The impedance adjustment unit is coupled to the first regulator, and operates to cause the first regulator to provide a second power signal having a power level different from that of the first power signal.

Level shifting module and power circuit and method of operating level shifting module

A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.

System and method for lithography alignment

Among other things, one or more systems and techniques for promoting metal plating uniformity are provided. An insulator plate is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. The insulator plate comprises an insulator ring that provides a resistance to electrical plating current passing through the insulator ring to the semiconductor wafer. The insulator plate comprises one or more porous regions, such as holes, that introduce little to no additional resistance to electrical plating current passing through such porous regions to the semiconductor wafer. The insulator plate influences electrical plating current so that edge plating current has a current value similar to a center plating current. The similarity in plating current promotes metal plating uniformity for the semiconductor wafer.

Insulator plate for metal plating control

An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

Power source for memory circuitry

A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

Decode switch and method for controlling decode switch

Growing community of inventors

Beipu, Taiwan

Chun-Yi Lee