Taiwan Semiconductor Manufacturing Comp. Ltd.

Hon Hai Precision Industry Co., Ltd.

Sino-American Silicon Products Inc.

Chun-Yen Peng

Chi On Chui

Sai-Hooi Yeong

Te-Yang Lai

Chih-Yu Chang

Bo-Feng Young

Huicheng Chang

Yi-Fan Chen

Cheng-Po Chau

Wen-Yu Ku

Hongfa Luan

Wen-Ching Hsu

Hao-Chung Kuo

Sai-hooi Yeong

Kun-Lin Yang

Bo-Wen Lin

Bo-Hsiang Tseng

Yi-Shan Hsieh

Wen-Chien Miao

Shih-Chen Chen

Hsin Chiang

Fu-He Hsiao

A micro LED display device includes a light emitting layer, a color conversion layer located on a light emitting surface of the light emitting layer, and a Bragg reflection element located on the color conversion layer. The Bragg reflection element includes a plurality of layer pairs. Each of the layer pairs includes at least one first layer and at least one second layer alternately stacked. The layer pairs include a top layer pair, a bottom layer pair and a plurality of middle layer pairs between the top layer pair and the bottom layer pair. A thickness of the first layer of each of the middle layer pairs is smaller than a thickness of the second layer of each of the middle layer pairs. A refractive index of the first layer is greater than a refractive index of the second layer.

Micro LED display device

A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

Dipole-engineered high-k gate dielectric and method forming same

The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Semiconductor structure and manufacturing method for the semiconductor structure

A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

Semiconductor devices devices including crystallized layer having multiple crystalline orientations and methods of manufacture

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO(BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.

Metal insulator metal (MIM) structure and manufacturing method thereof

The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.

Semiconductor device and manufacturing method for the semiconductor device

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices

Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Method of forming a semiconductor device by driving hydrogen into a dielectric layer from another dielectric layer

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions may be modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.

Semiconductor device and method of manufacture

Semiconductor devices and methods of manufacture

A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to a base portion of the bottom electrode layer. The bottom electrode layer includes the base portion and a plurality of protrusions, each of the protrusions is protruding from the base portion and leveled with a lower surface of the dielectric layer, each portion of the dielectric layer over the bottom electrode layer substantially have identical thicknesses.

The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion and the total volume of the first portion is greater than a total volume of the third portion.

Growing community of inventors

Hsinchu, Taiwan

Chun-Yen Peng