United Microelectronics Corp.

National Science Council

Chun Yen Chang

Joe Ko

Hsiao-Yi Lin

Jih W Chou

Po-Sheng Shih

Ting-Chang Chang

Heng-Sheng Huang

Tan-Fu Lei

Jz-Jan Jeng

Ci-Lin Pan

A method for manufacturing a magnetic field transducing device is provided which includes (a) providing a substrate, (b) subjecting the substrate to a semiconductor device fabricating process in order to obtain a magnetic field transducer, (c) forming an oxide over the magnetic field transducer and (d) covering a magnetic film on the oxide in order to obtain the magnetic field transducing device. The semiconductor device fabricating process also includes (b1) utilizing a mask photolithography etching process to form an annular groove on the substrate, (b2) covering a first insulating layer on the substrate and using a second mask photolithography etching process to form a plurality of diffusing openings on the first insulation layer, (b3) forming extrinsic semiconductor region on the substrate exposed by the plurality of diffusing openings, (b4) forming a second insulation layer on the substrate, (b5) utilizing a third mask photolithography etching process to form a plurality of contacts on the extrinsic semiconductor region, and (b6) forming a conductor on the substrate in order to form a connecting line. The magnetic film is preferably made of Ni and Co.

Method of manufacturing magnetic field transducer with improved sensitivity by plating a magnetic film on the back of the substrate

The invention provides a method for manufacturing a transistor having a low leakage current. In general, spacers must be formed to isolate a gate from a subsequently-formed drain, thereby reducing a leakage current. In the invention, the spacers are formed on the vertical sides of the gate by using a selective deposition process. Therefore, the method for manufacturing a transistor having a low leakage current according to the invention not only constitutes a simplified process, but also controls the widths of the spacers precisely, so that the leakage current of the transistor can be greatly decreased.

Method for manufacturing a transistor having a low leakage current

A GaAs-InGaAs high electron mobility transistor includes: a GaAs substrate; a GaAs buffer layer overlaying on the GaAs substrate; a graded InGaAs channel overlaying on the GaAs layer; a GaAs spacer layer overlaying on the graded InGaAs channel layer; a .delta.-doping layer overlaying on the GaAs spacer layer; a GaAs cap layer overlaying on the .delta.-doping layer; drain and source terminals overlaying on the GaAs cap layer and contacting the graded InGaAs channel layer; and a gate terminal overlaying on the GaAs cover layer and located between the drain terminal and the source terminal.

Method for making GaAs-InGaAs high electron mobility transistor

A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

Surface counter doped N-LDD for high carrier reliability

An FET thin film transistor is formed with a channel formed of a Si/Si.sub.1-x Ge.sub.x /Si three layer sandwich which serves as the carrier transfer channel. The percentage of germanium is preferably less than 30% and should be less than about 50%. The TFT can be structured as top gate, bottom gate or twin gate structure. The Si/Si.sub.1-x Ge/Si sandwich layer is processed in a continuous process under computer control.

Method of manufacturing super channel TFT structure

A method of forming an integrated circuit field effect transistor with surface counter-doped lightly doped drain regions is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

Growing community of inventors

Hsinchu, Taiwan

Chun Yen Chang