National Science Council

National Yang Ming Chiao Tung University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

United Microelectronics Corp.

National Taiwan Normal University

Phison Electronics Corporation

Himax Technologies, Inc.

Design Express Limited

Industrial Technology Research Institute

Au Optronics Corporation

Globalwafers Co., Ltd.

Witty Mate Corporation

Chun-Yen Chang

Yu-Tien Shen

Liang-Yin Chen

Chia-Cheng Chen

Ya-Hui Chang

Wei Hung Lin

Chih-Kai Yang

Hsiang-Ming Chang

Chung-Yuan Lee

Wei-Ting Chien

Horng-Chih Lin

Kuo-Yi Cheng

Chun-Hu Cheng

Yu-Chien Chiu

Yee-Chia Yeo

Huicheng Chang

Sun-Chieh Chien

Ting-Chang Chang

Ya Hui Chang

Chun-Hung Wu

Chi-Chun Chen

Hao-Chung Kuo

Hsiao-Yi Lin

Tsung-Hsi Yang

Tiao-Yuan Huang

Tan-Fu Lei

Du-Zen Peng

Che-Wei Chiang

Shao-Chin Chang

Shiang-Shiou Yen

Wei-Kai Liou

Chih-Hao Wang

Shih-Ming Chang

Chen-Chiu Hsue

Yen-Ping Wang

Po-Min Tu

Yen-Chen Chen

Yu-Cheng Hsu

Edward Yi Chang

Tung-Po Chen

Chih-Liang Pan

Zhen-Yu Li

Wei-Chi Lai

Tzung-Lin Li

Chung-Liang Lee

Jian-Shihn Tsang

Hao-Zhi Lee

Kuei-Ann Wen

Yu-Tse Lai

Jan-Dar Guo

Chen-Chiu Hsu

Kim-Hon Wong

Kazumitsu Nakamura

Liang-Po Chen

Guangli Luo

Tsung Hsi Yang

Han-Chang Cheng

Yeong-Lin Lai

Shih-Hciung Chan

Hsin-Chih Wang

Ping-Han Cheng

Chen-Yu Li

Juing-Yi Cheng

Hung-Ping D Yang

Rico Chang

Chien Liu

Charles Tijus

Mei-Fen Chou

Hung-Chun Lin

Jet-Rung Chang

Tsung-Yeh Yang

Wu-Ching Chou

Chu-Shou Yang

A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

System and method for multiple step directional patterning

A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

Critical dimension uniformity (CDU) control method and semiconductor substrate processing system

The invention discloses a computer aided design system and method for an educational table game. A plurality of predetermined objects, a plurality of predetermined hierarchical subjects, a plurality of predetermined learning contents, a plurality of predetermined game rule templates, a plurality of predetermined game scene templates, and a plurality of predetermined game accessory templates are previously provided. For the educational table games, a selected object is selected from the predetermined objects is selected, and a selected hierarchical subject is selected from the predetermined hierarchical subjects. Then, at least one selected learning content is selected. Next, a set game rule is set. Afterward, a set game scene is set. Then, a set game accessory package file is set. Finally, a game plan file is generated, and the game plan file and the set game accessory package file are output.

Computer aided design system and method for educational table games

A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Method of forming a semiconductor device

The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.

Etch apparatus for compensating shifted overlayers

A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Method for fabricating semiconductor device

A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Flash memory structure and method of manufacturing the same

A method of making a semiconductor device includes:

Method of making a semiconductor device

A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source and the drain are respectively disposed at two sides of the barrier layer. The p-type nitride layer is disposed on the barrier layer. The strain gate is disposed over the p-type nitride layer for tuning a first strain of the channel layer and a second strain of the barrier layer.

Semiconductor device and method of manufacturing the same

A magnetic capacitor includes a first electrode layer formed by depositing a first conducting material including graphene, a second electrode layer formed by depositing a second conducting material including graphene, and an insulator layer located between the first electrode layer and the second electrode layer. The magnetic capacitor further includes a first magnetized layer that includes one or more first ferro-magnetic elements that are magnetized to apply a first magnetic field to the insulator layer, and a second magnetized layer that includes one or more second ferro-magnetic elements that are magnetized to apply a second magnetic field to the insulator layer. The insulator layer is located between the first magnetized layer and the second magnetized layer. The first magnetic field and the second magnetic field improve a first electrical property of the magnetic capacitor.

High energy density and low leakage electronic devices

A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

Field effect transistor structure with gate structure having a wall and floor portions

A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Three-dimensional non-volatile memory structure and manufacturing method thereof

The invention discloses a social networking system which includes a main data processing apparatus, a plurality of smart clothing apparatus and a plurality of sub-data-processing apparatuses. Each smart clothing apparatus includes a light-emitting device assembly. Each sub-data-processing apparatus corresponds to one of the smart clothing apparatuses. The main data processing apparatus transmits an inquiry information to each sub-data-processing apparatus. The inquiry information includes a plurality of selection data and a plurality of light color data. Each selection datum corresponds to one of the light color data. Each sub-data-processing apparatus receives the inquiry information, displays the plurality of selection data, and transmits, responsive to a selection signal corresponding to one of the selection data, the light color datum corresponding to said one selection datum to the corresponding smart clothing apparatus. The corresponding smart clothing apparatus drives the light-emitting device assembly thereof to emit at least one color light in accordance with the received light color datum.

Social networking system based on smart clothing

Growing community of inventors

Hsinchu County, Taiwan

Chun-Yen Chang