Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Yao Wang

Chi On Chui

Kun-Yu Lee

Tze-Liang Lee

Tai-Chun Huang

Tsai-Fu Hsiao

A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has a U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Semiconductor device and method for forming the same

A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

A wafer processing chamber is provided, including a first processing gas supply unit and a second processing gas supply unit. The first processing gas supply unit is configured for supplying a first processing gas to form a first processing zone in the wafer processing chamber. The second processing gas supply unit is configured for supplying a second processing gas into the wafer processing chamber to form a second processing zone in the wafer processing chamber. In the wafer processing chamber, the first processing zone and the second processing zone are virtually separated from each other, such that a process wafer in the first processing zone may be performed a different process from another process wafer in the second processing zone at the same time. Further, a heat treatment apparatus and a method for processing wafers also provide herein.

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Zhubei, Taiwan

Chun-Yao Wang