United Microelectronics Corp.

Other

Koninklijke Philips Corporation N.v.

Chun-Wei Hsu

Chia-Lin Hsu

Chih-Hsun Lin

Yen-Ming Chen

Chang-Hung Kung

Teng-Chun Tsai

Po-Cheng Huang

Chin-Cheng Chien

Tsuo-Wen Lu

Shu-Yen Chan

Yu-Ting Li

Chia-Lung Chang

Jei-Ming Chen

Yu-Min Lin

Jie-Ning Yang

Tzung-Ying Lee

Ren-Peng Huang

Yu-Ren Wang

Chun-Ting Chou

Chien-Liang Lin

Ying-Wei Yen

Shao-Wei Wang

Wen-Yi Teng

Yi-Ching Wu

Chih-Chung Chen

Wu-Sian Sie

Chun-Hsiung Wang

Wei-Che Tsao

Kuang-Tsan Hung

Yi Chen

Chia-Hsi Chen

Chia-His Chen

A method for deterministic directional discovery of neighbor devices by a device in a wireless network comprises dividing equally an access time to a discovery channel to predefined number of sector scanning periods (), wherein each sector scanning period includes a predefined number of discovery sweep periods (), and each discovery sweep period includes a predefined number of time slots (); scanning the discovery channel in a single sector during a current sector scanning period (S); transmitting a discovery frame towards each sector during each time slot of each discovery sweep period of the current sector scanning period (S); checking if at least one response to a transmitted discovery frame has been received during the current sector scanning period (S); and setting the device to scan the discovery channel in a next sector during a next sector scanning period, thereby sequentially accessing the predefined number of sector scanning periods (S).

Method and device for deterministic directional discovery of wireless devices

A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Manufacturing method for a shallow trench isolation

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.

Semiconductor device

A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.

Semiconductor device with lower metal layer thickness in PMOS region

A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

Semiconductor process

A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.

Semiconductor device having metal gate and manufacturing method thereof

A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Metal oxide semiconductor transistor and method of manufacturing the same

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Manufacturing method for metal gate using ion implantation

A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

Poly opening polish process

An overheat and overload sensing device includes a thermal sensor (such as a thermal regulator) and a breaker connected in parallel and used to cut off a power supply in case of current overload. The thermal sensor usually disposed near a heat source can respond automatically to cut off a local circuit in time in the case of overheat that will make the breaker become overloaded to break off power supply.

Overheat and overload sensing device

Growing community of inventors

Taipei, Taiwan

Chun-Wei Hsu