Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Wei Hsu

Jiun-Lei Jerry Yu

Fu-Wei Yao

Fu-Chih Yang

Chen-Ju Yu

King-Yuen Wong

Chi-Jen Liu

Liang-Guang Chen

Chih-Wen Hsiung

Chun Lin Tsai

Yi-Sheng Lin

Po-Chih Chen

Kei-Wei Chen

Chia-Wei Ho

Chi-Hsiang Shen

Yang-Chun Cheng

Pinlei Edmund Chu

Ling-Fu Nieh

William Weilun Hong

Li-Chieh Wu

Ting-Hsun Chang

Tsai-Hao Hung

Ying-Hsun Chen

Te-Ming Kung

Ji Cui

Chung-Yu Lin

Jian-Ci Lin

Mei-Yun Wang

Fu-Kai Yang

Kuo-Yi Chao

Chao-Hsun Wang

Kuo-Hsiu Wei

Chu Fu Chen

Kao-Feng Liao

Peng-Chung Jangjian

Chun Hao Liao

Chia Hsuan Lee

Chia-Cheng Pao

Cheng-Chun Chang

Pang-Sheng Chang

Chih-chieh Chang

Hui-chi Huang

Ru-Yi Su

Jen-Hao Yeh

Chun-Lin Tsai

Ker Hsiao Huo

Tang-Kuei Chang

Wei-Wei Liang

Jeng-Chi Lin

Fu-ming Huang

A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.

Semiconductor device cleaning solution, method of use, and method of manufacture

A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Composition and method for polishing and integrated circuit

An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

Integrated circuit photodetector

A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. A suction system removes pad conditioner debris and the slurry from the pad.

System and method for removing debris during chemical mechanical planarization

A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

Slurry composition and method for polishing and integrated circuit

The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

Method of forming a high electron mobility transistor

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Metal heterojunction structure with capping metal layer

A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.

Slurry composition, semiconductor structure and method for forming the same

A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Polishing interconnect structures in semiconductor devices

The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

Semiconductor structure and manufacturing method thereof

A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

A chemical mechanical polishing (CMP) system includes a polishing pad configured to polish a substrate. The CMP system further includes a heating system configured to adjust a temperature of the polishing pad. The heating system comprises at least one heating element spaced apart from the polishing pad. The CMP system further includes a sensor configured to measure the temperature of the polishing pad.

External heating system for use in chemical mechanical polishing system

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Taichung, Taiwan

Chun-Wei Hsu