Compal Electronics, Inc.

Seriphy Technology Corporation

Chun-Wei Chang

Shang-Pin Chen

Wei-Chih Chen

Tsung-Hsuan Tsai

Che-yen Huang

Tzu-wei Chiu

Yong-Cheng Chen

The present disclosure provides a base station load balancing system including a communication network, a performance evaluator and an algorithm switching device. The communication network includes a base station and a plurality of user devices. The performance evaluator is connected to the communication network and evaluates a loading performance of the communication network in a time period according to a first loading data of the communication network in the time period. The algorithm switching device is connected to the performance evaluator and selects the algorithm used by the communication network as a selected algorithm according to the loading performance. The communication network, with the selected algorithm, allocates the connection relation between the base station and plurality of user devices according to the first loading data. The selected algorithm is a machine learning algorithm or a rule-based algorithm.

Base station load balancing system and method

The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Semiconductor structure and semiconductor device

Growing community of inventors

Taipei, Taiwan

Chun-Wei Chang