Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Htc Corporation

Hon Hai Precision Industry Co., Ltd.

Epistar Corporation

Au Optronics Corporation

E Ink Holdings Inc.

Xintec Corporation

National Health Research Institutes

Other

Astec International Limited

Acer Inc.

Lite-on Technology Corporation

National Yang Ming Chiao Tung University

National Taipei University of Technology

Chun-Wei Chang

Feng-Jia Shiu

Ching-Sen Kuo

Chih-Chien Wang

Wei-Chao Chiu

Dun-Nian Yaung

Wang-Pen Mo

Sheng-Feng Liu

Hung-Chang Hsieh

Wei-Cheng Hsu

Clement Hsingjen Wann

Neng-Kuo Chen

Jiaw-Ren Shih

Sey-Ping Sun

Yi-An Lin

Kai Tzeng

Ching-Chun Wang

Jhy-Jyi Sze

Shyh-Fann Ting

Jen-Cheng Liu

Yeur-Luen Tu

Feng-Chi Hung

Chen-Jong Wang

Chen Ou

Yimin Huang

Szu-Lin Liu

Jian-Hong Lin

Wei Chuang Wu

Jhong-Sheng Wang

Seiji Takahashi

Amit Kundu

Hsien Yu Tseng

Cheng-Hsien Chou

Tzu-Hsuan Hsu

Tsang-Yu Liu

Sheng-Chau Chen

Chih-Wei Wu

Hsiao-Hui Tseng

Chih-Yu Lai

Shih Pei Chou

Yu-Wen Chen

Chien-Hui Chen

Jing-Ping Liou

Yen-Cheng Lin

Hsing-Pang Hsieh

Pei-Lin Huang

Kai-Chun Hsu

Jang-Yang Chang

Ching-Chih Li

Jie-Chuan Huang

Chia-Chen Tsai

Cheng-Ta Wu

Yi-Ming Chen

Chia-Ming Cheng

Chun-Chang Chen

Ming-Yih Wang

Ang-Sheng Lin

Chih-hao Hsu

Mingni Chang

Ming-Hong Hsieh

Yung-Sheng Tsai

Bi-Ling Lin

Yung-Huei Lee

Hsien-Chang Lin

Shou-En Liu

Pei-Chun Liao

Hsuan-Ming Huang

Chia-Shiung Tsai

Yu-Lien Huang

Shu-Ming Chang

Jiech-Fun Lu

Yen-Shih Ho

Chi-Ming Wu

Chun-Yu Lin

Shih-Chang Lee

Chia-Sheng Lin

Sung-Yu Su

Yien-Chun Kuo

Wen-Luh Liao

Wu-Chen Lee

Nan-Jang Chen

Yi-Ping Lin

Nan-Cheng Chen

Sea-Fue Wang

Shun-Bin Chen

Ian French

Shang-Pin Chen

Sheng-Ming Chang

Chia-Chieh Lin

Shu-Hao Huang

Yuan-Cheng Lai

Rong-Fu Lin

Chung Chien Wang

Sheng-Chieh Lin

Wei-Ting Hsiao

Che-Yuan Jao

Song-Yu Yang

Chun-Neng Liao

Kuei-Wei Chen

Yun-I Liu

A module connector comprising a first connecting component and a second connecting component. The first connecting component includes a first base, a plurality of first conductors and a plurality of first clamping parts. The first base includes a first body, a plurality of first cable grooves, a plurality of first through holes and a plurality of third cable grooves. The first body forms the first cable grooves and the third cable grooves to be able to accommodate the cables. The central axes of the first through holes are at a first angle with the first cable grooves and pass through the first body, and one ends of the first through holes communicate with the first cable grooves. The first conductors are disposed in the first cable grooves. The second connecting component can connect with the first connecting component through the cables, so that at least one of signals and power can be transmitted between the second connecting component and the circuit board.

Module connector

A semiconductor device includes a semiconductor stack, a third semiconductor structure, a dielectric layer, and a reflective layer under the third semiconductor structure. The semiconductor stack includes a first semiconductor structure, an active structure, a second semiconductor structure. The first semiconductor structure has a first surface which includes a first portion and a second portion, and the first surface has a first area. The third semiconductor structure connects to the first portion, and has a second surface with a second area. The dielectric layer connects to the second portion and includes a plurality of openings, and the plurality of openings have a third area. A ratio of the second area to the first area is between 0.1˜0.7, and a ratio of the third area to the first area is less than 0.2.

Semiconductor device

A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.

Phase-change memory cell and method for fabricating the same

Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Techniques for forming a deep trench isolation structure between photodiodes by forming a first set of trenches based on a first pattern and forming a second set of trenches based on a second pattern

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Semiconductor structure and method of manufacturing the same

A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.

Semiconductor device and semiconductor component including the same

An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Electromigration evaluation methodology with consideration of both self-heating and heat sink thermal effects

Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Implantation mask formation

A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height.

Fin field effect transistor (FinFET) device having position-dependent heat generation

In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

Semiconductor imaging device having improved dark current performance

A method includes performing a first lithography process using a first pattern of a first photomask to form a first photoresist pattern on a front side of a device substrate; performing a first implantation process using the first pattern as a mask to form first isolation regions in the device substrate; after performing the first implantation process, performing a second lithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being shifted from the first pattern by a distance less than the first pitch and in the first direction; performing a second implantation process using the second photoresist pattern as a mask to form second isolation regions in the device substrate and spaced apart from the first isolation regions; and forming pixels between the first and second isolation regions.

Image sensor device and manufacturing method thereof

The present invention discloses a buckle connector connecting a main board and a sub-board. The buckle connector includes a first connecting portion and a second connecting portion. The first connecting portion mainly provides a first coupling member and the second connecting portion mainly provides a second coupling member. The first connecting portion and the second connecting portion are disposed on the same plane by coupling the first coupling member and the second coupling member when the first connecting portion moves to the second connecting portion in one direction.

Buckle connector

A head-mounted display device assembly and an external adjustment module are provided. The head-mounted display device assembly includes a head-mounted display device and the external adjustment module. The head-mounted display device has a first lens and a second lens corresponding to both eyes, and also has a driven mechanism. The first lens and the second lens are respectively coupled to the driven mechanism. The external adjustment module is used for assembling and electrically connecting to the head-mounted display device, and includes a driving element and a transmission element. In a coupling state, the transmission element is coupled to the driving element and the driven mechanism, and the driving element drives the driven mechanism via the transmission element to adjust a distance between the first lens and the second lens. In a separation state, at least one of the driving element and the driven mechanism is separated from the transmission element.

Head-mounted display device assembly and external adjustment module

Growing community of inventors

Taoyuan, Taiwan

Chun-Wei Chang