Ati International Srl

Broadcom Corporation

Ati Technologies Inc.

Qualcomm Incorporated

Ati Technologies Ulc

Chun Wang

Philip L Swan

Richard Sita

Raymond M Li

Paul Chow

Adrian H Hartog

Daniel Gudmundson

Edward George Callway

Carl K Mizuyabu

David A Strasser

Kevork Kechichian

Kumar Samir Saurabh

Anthony Chan

Gabriel Varga

Sreekanth Modaikkal

Allen J C Porter

Glen Timothy McDonnell

Youjing Zhang

Babs L Carter

Ilya Klebanov

Jonathan Wicks

Kalyan Thota

Mark Sternberg

Daniel Stan

Ivan W Y Yang

Vishnuvardhan Prodduturi

Ed Callway

Allen Jc Porter

Samson Kim

Kit Fong Ng

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.

Power efficient display architecture

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for synchronized dual eye variable refresh rate update for a VR display. A display processor obtains an indication of a synchronous flush or an asynchronous flush with respect to a first DPU and/or a second DPU. The display processor determines whether a first flush operation and/or a second flush operation is available at a time instance, where the first flush operation and the second flush operation are associated with the first DPU and/or the second DPU. The display processor performs, based on a VSync instance, the first flush operation and/or the second flush operation based on whether the first flush operation and/or the second flush operation are available at the time instance and based on the indication of the synchronous flush or the asynchronous flush.

Synchronized dual eye variable refresh rate update for VR display

The present disclosure relates to methods and devices for display processing. The device can receive a first image including a plurality of first pixels. Each of the first pixels can include a first red, green, blue (RGB) color value. The device can also determine an RGB adjustment value based on a lens correction value. Additionally, the device can determine a second RGB color value for each first pixel based on the determined RGB adjustment value. The device can also generate a second image including a plurality of second pixels, where each of the second pixels includes a determined second RGB color value. Moreover, the device can separate at least one of a red color value, green color value, or blue color value of the RGB color value and adjust at least one of a red color value or a blue color value based on the lens correction value.

Methods and apparatus for inline chromatic aberration correction

A video decoder block provides a common pathway for processing video signals encoded using different video formats. The video decoder block passes the video signals through the same processing components in order convert the signals to a common format for display or storage. Each processing component cat be disabled or by-passed to enable or disable the function performed by the component. This reduces the number of components and signal processors required in devices that need to accommodate signals of different formats.

Video decoder block

A video decoder block provides a common pathway for processing video signals encoded using different video formats. The video decoder block passes the video signals through the same processing components in order convert the signals to a common format for display or storage. Each processing component can be disabled or by-passed to enable or disable the function performed by the component. This reduces the number of components and signal processors required in devices that need to accommodate signals of different formats.

A method and apparatus for storing a compressed video stream or an uncompressed video stream is disclosed. The uncompressed video stream may be ZOOM VIDEO data. The compressed video stream may be a TRANSPORT STREAM data from a High Definition Television (HDTV) broadcast. A video graphics adapter is configured to properly receive one of the two types of video data. The received data and control signals are monitored to provide a second set of control of data signal which are used by a packer and an window control to provide data of a predetermined width and control to an address generator. The data is buffered within a graphics memory such as a frame buffer. The graphics memory can be written to system memory when full, or accessed by the system memory controller during the fill operation if a multi-ported memory is used.

Method and apparatus for receiving digital video signals

A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Memory controller for handling multiple clients and method thereof

A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Method and apparatus for maintaining secure and nonsecure data in a shared memory system

The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention provides increased performance in the system. The memory and I/O bridge can include a deep memory access request FIFO to queue up memory access requests when the memory controller is busy. The memory and I/O bridge can include a memory write data buffer for holding and merging memory write operations to the same page of memory. The memory and I/O bridge can include a memory read data buffer for holding and queuing data and instructions read from memory, waiting to be forward to the data bus. The memory data read buffer can operate in one or more software selectable prefetch modes, which can cause one or more pages to be read in response to a single memory read instruction. The memory read data buffer can satisfy memory read request for data or instructions already held in the memory read buffer without reading the data or instructions from memory. The memory read data buffer can also provide for data coherency with respect the memory write data buffer and the external memory. The memory and I/O bridge can also include performance counters for tracking information about the performance of the memory and I/O bridge in order to tune the software operation and determine the optimum prefetch mode for a given application.

Memory and I/O bridge

System for testing multiple devices on a single system and method thereof

A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.

Tiled memory configuration for mapping video data and method thereof

A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Display FIFO memory management system

A method and apparatus for allocation and control of memory bandwidth within a video graphics system is accomplished by first determining the memory bandwidth needs of each of the plurality of memory clients in the video graphics system. Based on this determination, a plurality of timers are configured, wherein each of the timers corresponds to one of the plurality of memory clients. The timers associated with the memory clients store two values. One value indicates the memory access interval for the corresponding client, which determines the spacing between memory access requests that can be issued by that particular client. The other value stored in the time is a memory access limit value, which determines the maximum length of a protected access to the memory by that particular client. A memory controller in the system receives requests from the plurality of clients and determines the priority of the different requests. The memory controller grants the requests with the highest priority, which may result in the termination of a current memory access. However, if the current memory access has equal or greater priority than a received access, the current memory access will not be terminated until the time associated with its memory access limit has expired.

Method and apparatus for memory bandwith allocation and control in a video graphics system

A system and method employs a single port digital video and/or audio capture circuit that is responsive to digitized uncompressed digital video and/or audio data and vertical blanking interval (VBI) data. In one embodiment, the single port capture circuit employs a parsing circuit that parses received VBI data along with any other received data such as video data and/or audio data and serves as a memory control signal generator that generates a VBI memory control signal and at least one of a video memory control signal and/or audio memory control signal to facilitate storage of the parsed VBI data, video data and audio data (if present) into predefined distinct locations within a memory, such as a frame buffer. A write FIFO memory receives the video data, VBI data, video memory address data and VBI memory address data (and audio information if present) as a storage hold prior to being stored in the frame buffer.

Growing community of inventors

Toronto, Canada

Chun Wang