Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Tsung Kuo

Jiech-Fun Lu

Yen-Shuo Su

Chia-Shiung Tsai

Shih-Chang Liu

Yeur-Luen Tu

Chuan-Feng Chen

Dun-Nian Yaung

Ching-Chun Wang

Jhy-Jyi Sze

Ming Chyi Liu

Shyh-Fann Ting

Yu-Hung Cheng

Shih Pei Chou

Yi-Shin Chu

Wen-I Hsu

Ching-Chung Su

Min-Ying Tsai

Ching I Li

Kai-Chun Hsu

Chiao-Chun Hsu

Wei-Tung Huang

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a plurality of photodetectors disposed within a substrate, and the plurality of photodetectors includes a first active photodetector and a black level correction (BLC) photodetector. A metal grid structure surrounds the first active photodetector along a periphery of the first active photodetector on a first side of the substrate. A recessed blocking structure covers the BLC photodetector on the first side of the substrate. The recessed blocking structure includes both a first blocking layer inset into the first side of the substrate and a second blocking layer directly over the first blocking layer.

Recessed blocking structure for BLC pixels

A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

Bipolar junction transistors and methods of forming the same

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.

Ring structure for film resistor

A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.

Semiconductor structure and method of manufacturing the same

The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Back-side deep trench isolation structure for image sensor

Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.

Bipolar junction transistor (BJT) comprising a multilayer base dielectric film

Various embodiments of the present disclosure are directed towards an image sensor having a substrate including a plurality of sidewalls that define a plurality of protrusions along a first side of the substrate. The substrate has a first index of refraction. A photodetector is disposed within the substrate and underlying the plurality of protrusions. A plurality of micro-lenses overlying the first side of the substrate. The micro-lenses have a second index of refraction that is less than the first index of refraction. The micro-lenses are respectively disposed laterally between and directly contact an adjacent pair of protrusions in the plurality of protrusions. Further, the micro-lenses respectively comprise a convex upper surface.

Lens structure configured to increase quantum efficiency of image sensor

Various embodiments of the present disclosure are directed towards an integrated chip including a resistor structure. A resistive layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistive layer and conductive via structures overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structures to a second point below a bottom surface of the resistive layer.

A method includes depositing a magnetic layer over a dielectric layer, and etching a first portion of the magnetic layer, in which a second portion of the magnetic layer that is directly under the first portion of the magnetic layer remains over the dielectric layer after etching the first portion of the magnetic layer. The second portion of the magnetic layer is etched.

Method for fabricating magnetic core

A method for fabricating a magnetic core includes depositing a magnetic layer on a dielectric layer, forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer, etching the magnetic layer through the patterned first photoresist layer, in which a first section of the magnetic layer exposed by the first photoresist layer remains on the dielectric layer after the magnetic layer is etched, removing the patterned first photoresist layer, forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer, etching the magnetic layer through the patterned second photoresist layer, and removing the second photoresist layer.

A semiconductor device structure is provided. The semiconductor device structure includes a collector element formed in or over a semiconductor substrate. The semiconductor device structure also includes a semiconductor element over the collector element, and the semiconductor element has a top surface, a bottom surface, and a side surface. The semiconductor device structure further includes an emitter element over the top surface of the semiconductor element. In addition, the semiconductor device structure includes a base element over the collector element and in direct contact with the side surface of the semiconductor element.

Structure and formation method of semiconductor device with bipolar junction transistor

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes an active area on a substrate, where the active area is at least one of a p-type region or an n-type region. The substrate includes a well, where the well is a p-well when the active area is a p-type region, and the well is an n-well when the active area is an n-type region. The well includes a photodiode. The active area is connected to a voltage supply having a voltage level, such as ground. The active area on the substrate increases a distance between the photodiode and the active area, which reduces junction leakage as compared to a semiconductor arrangement where the active area is formed at least partially within the substrate.

Semiconductor arrangement and formation thereof

A magnetic core includes a center section having a substantially uniform thickness, and an edge section connected to and surrounding the center section. The edge section includes a bottom portion and a top portion disposed on the bottom portion, in which the bottom portion has a gradual side surface since the top portion has a steep side surface. The profile of the magnetic core can be more rectangular thereby providing better inductor performance.

Magnetic core, inductor, and method for fabricating the magnetic core

A method of forming a semiconductor device includes forming a lower coil segment in a first dielectric layer over a substrate, forming a second dielectric layer over the lower coil segment and the first dielectric layer, anisotropically etching a top portion of the second dielectric layer to form an opening over the lower coil segment, depositing magnetic material in the opening to form a magnetic core, forming a third dielectric layer over the magnetic core and the second dielectric layer, forming vias extending through the second dielectric layer and the third dielectric layer, and after forming the vias, forming an upper coil segment over the third dielectric layer and the magnetic core, wherein the vias connect the upper coil segment with the lower coil segment.

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Tainan, Taiwan

Chun-Tsung Kuo