United Microelectronics Corp.

Chun-Tsen Lu

Kun-Ju Li

Kuan-Hung Chen

Rung-Yuan Lee

Chung-Fu Chang

Po-Cheng Huang

Fu-Shou Tsai

Kuo-Chin Hung

Hsin-Jung Liu

Guang-Yu Lo

Yu-Ping Wang

Bin-Siang Tsai

Chen-Ming Huang

Fu-Yu Tsai

Min-Chuan Tsai

Yu-Ting Li

Tai-Cheng Hou

Chih-Yueh Li

Wei-Chuan Tsai

Chun-Chia Chen

Li-Chieh Hsu

Chau-Chung Hou

Wu-Sian Sie

Yu-Lung Shih

Ang Chan

Yi-Han Liao

Hsin-Yu Chen

Chien-Ming Lai

Shou-Wei Hsieh

Chun-Hao Lin

Ya-Huei Tsai

Wen-Chin Lin

Chih-Hsun Lin

Lu-Sheng Chou

Yu-Tung Hsiao

Ching-Hsiang Chiu

I-Lun Hung

Yu-Cheng Tung

En-Chiuan Liou

Ssu-I Fu

Chih-Kai Hsu

Shih-Fang Tzou

Yu-Hsiang Lin

Chin-Hung Chen

Chia-Jung Hsu

Shui-Yen Lu

Chun-Ya Chiu

Po-Wen Su

Yi-Wen Chen

Jen-Chieh Lin

Jui-Ming Yang

Yu-Ting Tseng

Tzu-Hsiang Hung

Mon-Sen Lin

Chun-Lin Chen

Hao-Yeh Liu

Chorng-Lih Young

Jian-Wei Chen

Shih-Ming Lin

Kun Ju Li

Hsin Jung Liu

Yi Han Liao

Lan-Ping Chang

Chih-Jung Su

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Semiconductor device and method for fabricating the same

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

Magnetoresistive random access memory and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

Method of manufacturing a semiconductor device

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

Vertical gate-all-around transistor and manufacturing method thereof

A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

Semiconductor device

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Semiconductor device with metal gate

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

Semiconductor device and manufacturing method thereof

A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

Conductive layout structure including high resistive layer

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a shallow trench isolation (STI) around the first fin-shaped structure; forming a first oxide layer on the first fin-shaped structure; and then forming a second oxide layer on the first oxide layer and the STI.

A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a recess in the fin structure so that the semiconductor substrate is partially exposed from the bottom surface of the recess; forming a dopant source layer conformally disposed on side surfaces and a bottom surface of the recess; removing the dopant source layer disposed on the bottom surface of the recess until portions of the semiconductor substrate are exposed from the bottom surface of the recess; and annealing the dopant source layer so as to form a side doped region in the fin structure.

Method of fabricating semiconductor device

Growing community of inventors

Tainan, Taiwan

Chun-Tsen Lu