Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Ting Wu

Ching-Hou Su

Chih-Pin Wang

Chun-Chiang Chen

An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.

Passivation layer for integrated circuit structure and forming the same

An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.

A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.

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Kaohsiung, Taiwan

Chun-Ting Wu