Realtek Semiconductor Inc.

Chun-Ta Ho

Shawn Min

Chun-I Kuo

Cheng-Yu Liu

Chuan-Ping Tu

Yi-Jang Wu

The present disclosure discloses a sample and hold amplifier circuit that includes a positive and a negative terminal capacitor arrays, a positive and a negative terminal switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal. In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a holding time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.

Sample and hold amplifier circuit

The present invention discloses a bias current generation circuit. An operation amplifier compares an input voltage having a zero-temperature coefficient and a feedback voltage to generate a driving voltage. An output transistor generates a bias current according to the driving voltage. A variable resistive circuit is electrically coupled to the output transistor through a feedback node to generate the feedback voltage according to the bias current and includes series-coupled resistors and switch transistors. Each of the resistors has a resistance having a positive temperature coefficient and includes a current input terminal and a current output terminal. Each of the switch transistors is electrically coupled between the current output terminal of one of the resistors and a ground terminal. One of the switch transistors turns on according to a control voltage variable according to the temperature variation to enable resistors to generate the resistance having a negative temperature coefficient.

Bias current generation circuit

A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.

Control chip supporting consumer electronics control protocol and high voltage tolerant output circuit thereof

A background self-calibrated DAC is presented. A virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized.

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Hsinchu, Taiwan

Chun-Ta Ho