United Microelectronics Corp.

Chun-Sung Huang

Shen-De Wang

Ping-Chia Shih

Chia-Ching Hsu

Chi-Cheng Huang

Wang Xiang

Chi Ren

Chih-Hung Lin

Ko-Chi Chen

Yau-Kae Sheu

Hsiang-Chen Lee

Chih-Ming Wang

Chiao-Lin Yang

Chin-Fu Lin

Liang Yi

Wen-Peng Hsu

Wei-Chang Liu

Chung-Che Huang

Yuan-Cheng Yang

Yu-Cheng Wang

Yung-Lin Tseng

A control gate is formed on the substrate. A source diffusion region is formed in the substrate and on a first side of the control gate. A select gate is formed on the source diffusion region. The select gate has a recessed top surface. A charge storage structure is formed under the control gate. A first spacer is formed between the select gate and the control gate and between the charge storage structure and the select gate. A wordline gate is formed on a second side of the control gate opposite to the select gate. A second spacer is formed between the wordline gate and the control gate. A drain diffusion region is formed in the substrate and adjacent to the wordline gate.

Semiconductor memory device and fabrication method thereof

A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.

A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

Memory device and method for fabricating the same

A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a-like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the-like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

Structure of semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

Semiconductor device and method for fabricating the same

A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

Memory structure

A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.

Semiconductor device with embedded cell and method of manufacturing the same

A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

Split gate non-volatile memory device and method for fabricating the same

A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.

Non-volatile memory cell and fabricating method thereof

A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.

SONOS non-volatile memory cell and fabricating method thereof

A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Method for manufacturing NAND memory cells

An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Method of etching oxide layer and nitride layer

A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

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Changhua County, Taiwan

Chun-Sung Huang